User Manual
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V 1.0
2021-08-25
XDPP1100 technical reference manual
Digital power controller
Digital pulse width modulator
Figure 57
External sync phase programming for non-bridge and bridge topologies
In order to synchronize to the external signal, various IO pins of the XDPP1100 can be used. These pins are BEN,
BPWRGD, EN, FAULT1, FAULT2, IMON, PWRGD, SMBALERT, SYNC and PWM1 through PWM12. Each pin has a
corresponding register
<pin_name>_func
(such as
fault1_func
, or
smbalert_func
) which needs to be set to a
value of 3 in order to map the corresponding pin to the external sync function. The direction of the external
sync function, input, or output, is defined by register
sync_dir_out
:
•
Set to 0 for sync input
•
Set to 1 for sync output
Multiple IO pins may be mapped as sync output simultaneously. When the sync function is defined as an input,
only one pin is actually used to receive the external sync pulse. If multiple pins are mapped to the sync
function, priority is given to the input with the lowest pin number. This priority order is: FAULT1, FAULT2, IMON,
PWM9, PWM10, PWM11, PWM12, PWM1, PWM2, PWM3, PWM4, PWM5, PWM6, PWM7, PWM8, SMBALERT, BEN,
BPWRGD, SYNC, EN and PWRGD.
ramp0
ramp1
SYNC
ramp0_phase
ramp1_phase
a) External sync on non-bridge topology (rampX_half_mode = 0)
ramp0
ramp1
SYNC
ramp0_phase
ramp1_phase
b) External sync on bridge topology (rampX_half_mode = 1)
