Infineon XDPP1100, Technical Reference Manual

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User Manual 345 of 562 V 1.0
2021-08-25
XDPP1100 technical reference manual
Digital power controller
Central processing unit subsystem
CPUS clock typical and maximum frequencies and related modules are shown in Table 93 .
Table 93 CPUS clock domains
Clock name Module name Typ. freq. (MHz) Max. freq. (MHz)
hosc_clk CGU 100 100
alpha_clk CGU 100 100
cpu_clk CPU (FCLK clock) 100 100
amba_clk AMBA domain 100 100
rom_clk ROM 100 100
ram1_clk RAM1 100 100
ram2_clk RAM2 100 100
dma_clk DMA 100 100
bif_reg_clk BIF REG 100 100
bif_per_clk BIF PER bridge 100 100
bif_per_svid_clk CRC32 peripheral 100 100
bif_per_pmbus BIF PER PMBus peripheral 100 100
bif_per_ssp_clk Not used – –
bif_per_i2c_clk
BIF PER I
2
C peripheral
100 100
bif_per_uart_clk BIF PER UART peripheral 100 100
cnfg_clk CPU APB PER bridge 100 100
cnfg_dma_clk DMA config. port 100 100
cnfg_otp1_w_clk OTP interface peripheral 100 100
otp_kernel_clk OTP kernel 25 100
apb_per_clk APB PER bridge 100 100
dtimer1_clk DTIMER1 peripheral 100 100
dtimer2_clk DTIMER2 peripheral 100 100
dtimer3_clk DTIMER3 peripheral 100 100
wdt_clk WDT interface clock 100 100
gpio0_clk GPIO0 peripheral 100 100
gpio1_clk GPIO1 peripheral 100 100
dtimer1_kernel_clk DTIMER1 kernel 100 100
dtimer2_kernel_clk DTIMER2 kernel 100 100
dtimer3_kernel_clk DTIMER3 kernel 100 100
wdt_kernel_clk WDT kernel 3.125 100
pmbus_kernel_clk PMBus kernel 25 100
15.3.2.1 Clock dividers
The CPUS clock structure includes eight programmable clock dividers ( Table 94 ).
The alpha clock is the root divider to scale the entire CPUS clock structure.
The CPU clock divider scales the Cortex®-M0 microcontroller and the AMBA® bus infrastructure.