User Manual 346 of 562 V 1.0
2021-08-25
XDPP1100 technical reference manual
Digital power controller
Central processing unit subsystem
The watchdog and timer clock dividers scale the counter clocks, keeping the interface on the AMBA® bus clock
unchanged, and allowing the time constant of the counters to be extended to bigger time intervals. This is
particularly effective for the watchdog, for example, where the timer interval is in the range of seconds.
The OTP kernel clock divider enables adjustment of the ratio of the OTP wrapper logic, which should work at a
nominal frequency of 25 MHz regardless of alpha clock speed.
The PMBus kernel clock divider enables adjustment of the ratio of the PMBus core logic with respect to alpha
clock frequency.
Table 94
CPUS clock dividers
Clock domain
Control register
Divider control
Description
alpha_clk
ALPHA_CLK_DIV_CTRL alpha_clk_div[4:0]
Root clock divider
cpu_clk
CPU_CLK_DIV_CTRL
cpuclk_div[4:0]
CPU core and bus clock
divider
wdt_kernel_clk
KRN_CLK_DIV_CTRL
wdt_kernel_clk_div[4:0]
Watchdog kernel counter
clock divider
pmbus_kernel_clk
KRN_CLK_DIV_CTRL
pmbus_kernel_clk_div[4:0]
PMBus logic core clock
divider
dtimer1_kernel_clk
KRN_CLK_DIV_CTRL
dtimer1_kernel_clk_div[4:0] D
TIMER1
counters clock divider
dtimer2_kernel_clk
KRN_CLK_DIV_CTRL
dtimer2_kernel_clk_div[4:0] D
TIMER2
counters clock divider
dtimer3_kernel_clk
KRN_CLK_DIV_CTRL
dtimer3_kernel_clk_div[4:0] D
TIMER3
counters clock divider
otp_kernel_clk
KRN_CLK_DIV_CTRL
otp_kernel_clk_div[4:0]
OTP kernel clock divider
All the programmable dividers can take any input divisor vector. The divisor should be programmed according
to the module’s required clock frequency. When divisor vector = 0, the function of
the divisor is
“
DIV by 1
”;
when
divisor vector = 1, the function of the divisor is
“
DIV by 2
”
and so on. In general xxx_clk_out = clk_in / (
1).
15.3.2.2
Clock gating
All the clock gating cells, with the exception of the primary-source clock gating, are based on the hierarchy
shown in
, where the last stage of gating is controlled by the clock enable register, and the previous
stage by the status of the Cortex®-M0 power state, defined by the signals SLEEPING and SLEEPDEEP (only
SLEEPDEEP will be used, as the GATEHCLK signal already takes into account the SLEEPING signal), if enabled in
the clock sleep and deep sleep mask configuration registers.
