User Manual 349 of 562 V 1.0
2021-08-25
XDPP1100 technical reference manual
Digital power controller
Central processing unit subsystem
Register name Field name
Access Address
Bits
Description
CPU_CLK_DIV_
CTRL
cpuclk_div
RW
4000_2004h [4:0]
This register configures the divider
of cpu_clk. The divide ratio is equal
to cpuclk_div[4:0] + 1. For example,
the reset setting cpuclk_div[4:0] = 0
generates a default clock frequency
of cpu_clk = alpha_clk/1.
KRN_CLK_DIV_
CTRL
dtimer1_kernel_clk
_div
RW
4000_2008h [4:0]
This register configures the divider
of the D
TIMER1
kernel clock. The
divide ratio is equal to
dtimer1_kernel_clk_div[4:0] + 1.
For example, the reset setting
dtimer1_kernel_clk_div[4:0] = 7
generates a default clock frequency
of dtimer1_kernel_clk =
alpha_clk/8.
KRN_CLK_DIV_
CTRL
dtimer2_kernel_clk
_div
RW
4000_2008h [9:5]
This register configures the divider
of the D
TIMER2
kernel clock. The
divide ratio is equal to
dtimer2_kernel_clk_div[4:0] + 1.
For example, the reset setting
dtimer2_kernel_clk_div[4:0] = 24
generates a default clock frequency
of dtimer2_kernel_clk =
alpha_clk/25.
KRN_CLK_DIV_
CTRL
dtimer3_kernel_clk
_div
RW
4000_2008h [14:10] This register configures the divider
of the D
TIMER3
kernel clock. The
divide ratio is equal to
dtimer3_kernel_clk_div[4:0] + 1.
For example, the reset setting
dtimer3_kernel_clk_div[4:0] = 7
generates a default clock frequency
of dtimer3_kernel_clk =
alpha_clk/8.
KRN_CLK_DIV_
CTRL
wdt_kernel_clk_div RW
4000_2008h [19:15] This register configures the divider
of the WDT kernel clock. The divide
ratio is equal to
wdt_kernel_clk_div[4:0] + 1. For
example, the reset setting
wdt_kernel_clk_div[4:0] = 0
generates a default clock frequency
of wdt_kernel_clk = alpha_clk/1.
KRN_CLK_DIV_
CTRL
pmbus_kernel_clk_
div
RW
4000_2008h [24:20] This register configures the divider
of the PMBus kernel clock. The
divide ratio is equal to
pmbus_kernel_clk_div[4:0] + 1. For
example, the reset setting
pmbus_kernel_clk_div[4:0] = 0
