Infineon XDPP1100, Technical Reference Manual

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User Manual 368 of 562 V 1.0
2021-08-25
XDPP1100 technical reference manual
Digital power controller
Central processing unit subsystem
Register name Field name Access Address Bits Description
0: Clock “ dtimer2_clk ” sleep state
clock gating status unchanged
1: Enable clock
“ dtimer2_clk ” sleep
state clock gating
CLK_SLEEP_M
SK_CNFG_SET se_dtimer3_clk_g W 4000_2038h [19] Enable dtimer3_clk clock gating
when the Cortex®-M0 enters sleep
state.
0: Clock
“ dtimer3_clk ” sleep state
clock gating status unchanged
1: Enable clock
“ dtimer3_clk ” sleep
state clock gating
CLK_SLEEP_M
SK_CNFG_SET se_wdt_clk_g W 4000_2038h [20] Enable wdt_clk clock gating when
the Cortex®-M0 enters sleep state.
0: Clock
“ wdt_clk ” sleep state clock
gating status unchanged
1: Enable clock
“ wdt_clk ” sleep
state clock gating
CLK_SLEEP_M
SK_CNFG_SET se_gpio0_clk_g W 4000_2038h [21] Enable gpio2_clk clock gating when
the Cortex®-M0 enters sleep state.
0: Clock
“ gpio2_clk ” sleep state
clock gating status unchanged
1: Enable clock
“ gpio2_clk ” sleep
state clock gating
CLK_SLEEP_M
SK_CNFG_SET se_gpio1_clk_g W 4000_2038h [22] Enable gpio1_clk clock gating when
the Cortex®-M0 enters sleep state.
0: Clock
“ gpio1_clk ” sleep state
clock gating status unchanged
1: Enable clock
“ gpio1_clk ” sleep
state clock gating
CLK_SLEEP_M
SK_CNFG_CLR se_hosc_clk_g W 4000_203Ch [0] Disable hosc_clk clock gating when
Cortex®-M0 will enter sleep state, if
the hosc_clk clock gating control
has been enabled. Warning: Only
external reset assertion can remove
clock gating if no external wakeup
source has been enabled before.
0: Clock
“ hosc_clk ” sleep state
clock gating status unchanged
1: Disable clock
“ hosc_clk ” sleep
state gating
CLK_SLEEP_M
SK_CNFG_CLR se_rom_clk_g W 4000_203Ch [1] Disable rom_clk clock gating when
the Cortex®-M0 enters sleep state.
0: Clock
“ rom_clk ” sleep state clock
gating status unchanged