User Manual 480 of 562 V 1.0
2021-08-25
XDPP1100 technical reference manual
Digital power controller
Central processing unit subsystem
Register name Field name
Access Address
Bits
Description
[0] Controls HPROT[1] to indicate if
a privileged access is occurring
Notes:
1. When bit[n]=1, then the
corresponding H
PROT
is high
2. When bit[n]=0, then the
corresponding H
PROT
is low
3. The CHN1_PROT_CTRL bits must
not be changed when the
MASTER_ENABLE bit is set because
this may cause a protocol error on
the AHB master interface. As the
DMA_CFG register is write-only, the
user must read the status of the
master enable bit from the
DMA_STATUS register.
DMA_CFG
RES1
W
5000_0004h [31:8]
Reserved, write as 0.
DMA_CTRL_BA
SE_PTR
CTRL_BASE_PTR
RW
5000_0008h [31:9]
Pointer to the base address of the
primary data structure.
DMA_ALT_CTR
L_BASE_PTR
ALT_CTRL_BASE_P
TR
R
5000_000Ch [31:0]
Returns the base address of the
alternate data structure.
CHNL_WAITON
REQ_STATUS
DMA_WAITONREQ_
STATUS
R
5000_0010h [15:0]
Channel wait on request status. For
each bit [x]:
0: DMA channel x wait on request is
low
1: DMA channel x wait on request is
high
DMA_CHNL_S
W_REQUEST
CHNL_SW_REQUES
T
W
5000_0014h [15:0]
The write-only CHNL_SW_REQUEST
register enables you to generate a
software DMA request. Set the
appropriate bit to generate a
software DMA request on the
corresponding DMA channel.
For each bit [x]:
0: Does not create a DMA request
for channel x
1: Creates a DMA request for
channel x
Note: Writing to a bit where a DMA
channel is not implemented does
not create a DMA request for that
channel.
DMA_CHNL_U
SEBURST_SET
CHNL_USEBURST_
SET
RW
5000_0018h [15:0]
Returns the use burst status, or
disables the single request
dma_sreq input from generating
DMA requests.
