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2021-08-25
XDPP1100 technical reference manual
Digital power controller
Compensator
6
Compensator
This chapter describes in more detail the XDPP1100 compensator implementation and main functionality. The
relevant user-programmable parameters and corresponding registers are discussed as well as the input FF
term and its relevant settings. Most of this chapter assumes that compensator output is directly the duty cycle
as in VMC, and in
PCMC and its relevant compensator-related register settings are shown. PCMC is
discussed in detail in the next chapter, and is therefore only briefly mentioned in this chapter.
The simplified block diagram of the compensator is shown in
, and it consists of:
•
Compensation filter, shown within the dashed lines
•
Input voltage FF function
These two main subfunctions of the compensator are described in more detail in the sections below.
Figure 45
Functional block diagram of the compensator
6.1
Compensation filter
This section describes the proportional-integral-derivative (PID) filter implementation in more detail as well as
its specific user-definable features and adjustments.
The compensation filter, inside the dashed lines in
, consists of:
•
PID filter
•
Pre- and post-LPFs
It receives as input the computed error signal, V
errn
, obtained from the VS processor, discussed in
The compensator output is the target duty cycle, utilized by the PWM to generate output pulses.
The transfer function implemented by the compensation filter is provided in Equation (6.1).
𝐷𝑢𝑡𝑦𝐶𝑦𝑐𝑙𝑒
𝑉𝑒𝑟𝑟𝑛
= [
𝐾
𝐹𝑃1
1−(1−𝐾
𝐹𝑃1
)𝑧
−1
] [(𝐾
𝑃
+ 𝐾
𝐷
(1 − 𝑧
−1
)) (
𝐾
𝐹𝑃2
1−(1−𝐾
𝐹𝑃2
)𝑧
−1
) +
𝐾
𝐼
1−𝑧
−1
] + 𝐹𝐹
(6.1)
The terms K
P
, K
D
and K
I
are the PID loop coefficients, and K
FP1,2
are the LPF coefficients which determine the
locations of the poles and zeros. The zero locations are defined by the coefficients K
P
, K
I
and K
D
, which are
programmed via following registers:
LPF1
LPF2
FF
+
I
PD
V
errn
K
FP1
K
P
K
FP2
K
I
V
control
V
RECT
Duty cycle
Compensation filter