User Manual 551 of 562 V 1.0
2021-08-25
XDPP1100 technical reference manual
Digital power controller
Central processing unit subsystem
Register name Field name
Access Address
Bits
Description
programmed to 1, the output is 0.
For DTE this can be used as ring
indicator (RI).
UARTCR
RTSEn
RW
700C_0030h [14]
RTS HW flow control enable. If this
bit is set to 1, RTS HW flow control
is enabled. Data is only requested
when there is space in the receive
FIFO for it to be received.
0: RTS HW flow control is disabled
1: RTS HW flow control is enabled
UARTCR
CTSEn
RW
700C_0030h [15]
CTS HW flow control enable. If this
bit is set to 1, CTS HW flow control
is enabled. Data is only transmitted
when the nUARTCTS signal is
asserted.
0: CTS HW flow control is disabled
1: CTS HW flow control is enabled
UARTIFLS
TXIFLSEL
RW
700C_0034h [2:0]
Transmit interrupt FIFO level select.
The trigger points for the transmit
interrupt are as follows:
0: Transmit FIFO becomes less than
1/8 full
1: Transmit FIFO becomes less than
1/4 full
2: Transmit FIFO becomes less than
1/2 full
3: Transmit FIFO becomes less than
3/4 full
4: Transmit FIFO becomes less than
7/8 full
5 to 7: Reserved
UARTIFLS
RXIFLSEL
RW
700C_0034h [5:3]
Receive interrupt FIFO level select.
The trigger points for the receive
interrupt are as follows:
0: Receive FIFO becomes more than
1/8 full
1: Receive FIFO becomes more than
1/4 full
2: Receive FIFO becomes more than
1/2 full
3: Receive FIFO becomes more than
3/4 full
4: Receive FIFO becomes more than
7/8 full
5 to 7: Reserved
