Infineon XDPP1100, Technical Reference Manual

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User Manual 394 of 562 V 1.0
2021-08-25
XDPP1100 technical reference manual
Digital power controller
Central processing unit subsystem
Table 98 OTP instructions for indirect access
Instruction
value Instruction Source/destination
register Description
5h01 PROG and VERIFY
Data taken from
DATAW0-4
Program and verify 128 bits into OTP
(complete write sequence: write,
read-back and, if necessary, soak)
5h02 READ
Data stored into
OTP_Q0-3
Read 128 bits from OTP
5h03
PROG
(basic transaction)
Data taken from
DATAW0-4
Perform a 128-bit WRITE basic
operation (no read-back, no
soaking)
5h04 WRITE OTP data register
Data taken from
DATAW0-4
Write OTP DR
5h05 SETMODE MRA
Data taken from
READ_MRAB
Write OTP MRA
5h06 CMP Perform a COMPARE basic operation
5h07 PCH
Perform a PRECHARGE basic
operation
5h08 BIST RESET Execute a BIST reset
5h09 BIST STRESS TEST Start a BIST stress test
5h0a BIST CLEAN ARRAY TEST Start a BIST clean array test
5h0b SETMODE MRB
Data taken from
READ_MRAB
Write OTP MRB
5h0c SETMODE MR
Data taken from
READ_MR
Write OTP MR
This is the register sequence to execute a 128-bit read:
•
Write OTP_ADDR and INSTRUCTION (0x2, READ) on INSTR register
•
Write something on EXEC register
•
Monitor STAT register:
o
APB_BUSY should rise and fall back to zero when the operation is completed
o
Read OTP returned value on OTP_Q0-3 registers
This is the register sequence to execute a 128-bit (OTP line) write and verify:
•
Write OTP_ADDR and INSTRUCTION (0x1, PROG and VERIFY) on which INSTR register
•
Write the data to be programmed on OTP into DATAW0-4 registers
•
Write something on EXEC register
•
Monitor STAT register:
o
APB_BUSY should rise and fall back to zero when the operation is completed
o
Error flags (SOAK_FAIL, RD2_FL and RD1_FL) must be low
There are two different operations to perform an OTP write: “PROG” and “PROG and VERIFY”