User Manual
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V 1.0
2021-08-25
XDPP1100 technical reference manual
Digital power controller
Voltage sense
The minimum pulse width (PW) of the deglitcher is programmable via register
vrs_min_pw
. If this deglitch
pulse is wider than the noise ringing pulse width, the false triggering is avoidable. It should be noted that if a
non-zero PW is programmed, the comparator output is delayed by the same amount and the tracking start
timer should be increased accordingly via register
vrs_track_start_thr
.
2.3.2.4
V
RECT
timing for two PWM signals
Previously, the V
RECT
timing was discussed in the case of a single PWM signal (
and
), utilized
typically in the ACF converter topology. However, in the bridge topologies, two PWM signals operate on
opposite cycles, referred to here as even and odd. The XDPP1100 measures and stores the PWM signals
separately, as shown in
Figure 13
VSP V
RECT
even and odd cycle timing
As previously discussed, the even and odd V
RECT
outputs are utilized by flux (volt-second) balancing function,
whereas the computed average is used by functions such as telemetry and FF.
2.3.2.5
V
IN
transient response
The response to input voltage transient is illustrated in
. If the transient is initiated prior to entering
the tracking window, the tracking ADC initially increases its step size in order to reach the moving input voltage.
Then it adjusts the step size downward, if necessary, to maintain the tracking. It might require several switching
cycles to complete the tracking to the settled input voltage. For V
RECT
sense, automatic step size is
recommended.
PWMe
VRSEN
vrs_comp_ref
vrs_comp
PWMo
vrs_vrect_even
vrs_vrect_odd
vrs_vrect
vrect_even[n]
vrect_even[n+1]
vrect_odd[n]
vrect_odd[n+1]
(vrect_even[n] + vrect_odd[n]) / 2
(vrect_even[n+1] + vrect_odd[n]) / 2
