User Manual 539 of 562 V 1.0
2021-08-25
XDPP1100 technical reference manual
Digital power controller
Central processing unit subsystem
Register name Field name
Access Address
Bits
Description
this state, the CNTR.STP bit must be
set and the CNTR.IFLG bit cleared.
The peripheral will then return to
idle state (status code F8h) and no
STOP condition will be transmitted
on the I
2
C bus. Note: To request
resumption of transmission, set the
STA bit to
“
1
”
at the same time as the
STP bit is set. The peripheral will
then send a START on recovery from
the bus error.
STAT_CCR
M
W
700B_000Ch [6:3] Along with STAT_CCR.N, controls the
frequency at which the I
2
C bus is
sampled and the frequency of the
clock line (SCL) when in master
mode.
F
samp
= F
clock
/ 2
N
F
SCL
= F
clock
/ (2
N
* (M+1) * 10)
where F
clock
is the frequency of the I
2
C
peripheral clock input.
XADDR
SLAX
RW
700B_0010h [7:0] Extended slave address bits [7:0]
(SLAX7..SLAX0). When
ADDR.SLA[4:0]=11110b, the I
2
C
peripheral recognizes this as the first
part of a 10-bit address and if the
next two bits match ADDR.SLAX[1:0]
it sends an ACK. If the next byte of
the address matches
XADDR.SLAX[7:0] the I
2
C peripheral
generates an interrupt and goes into
slave mode.
SRST
RST
W
700B_001Ch [6:0] Software reset. A software reset of
the I
2
C peripheral is applied upon
writing any value to this register. A
software reset sets the peripheral
back to IDLE (STAT.CODE=F8h) and
sets the STP, STA and IFLG bits in the
CNTR register to
“
0
”
.
15.12
CRC module
The CRC module is a HW accelerator to support FW CRC calculations. The CRC module is implemented in a
general-purpose way through configuration registers, in order to allow high configurability of the algorithm
that needs to be realized.
The CRC module supports:
