User Manual
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V 1.0
2021-08-25
XDPP1100 technical reference manual
Digital power controller
Compensator
Peripheral Field name
Access Address
Bits
Description
7000_2004h
(pid1)
ki_man = 8 + pid_ki_index_1ph[2:0]
ki = ki_man * 2^ki_exp * 2^-25
pid
pid_kd_index_1ph
RW
7000_1C04h
(pid0)
7000_2004h
(pid1)
[30:24] PID derivative coefficient index.
Note that index settings greater
than 119 are clamped to 119.
kd_exp = pid_kd_index_1ph[6:3]
kd_man = 8 +
pid_kd_index_1ph[2:0]
kd = kd_man * 2^kd_exp * 2^-10
pid
pid_force_duty
RW
7000_1C08h
(pid0)
7000_2008h
(pid1)
[7:0]
Forced duty-cycle value overrides
the PID output when selected by
pid_force_duty_en. Since this force
is applied at the PID output,
downstream adjustments to the
duty cycle such as current balance
in an interleaved (multiphase)
design are still applied. To also
override the current balance adjust
use pwm.ramp0_force_duty or
pwm.ramp1_force_duty.
LSB = 2^-8, range = 0.0 to 0.9961
pid
pid_force_duty_en
RW
7000_1C08h
(pid0)
7000_2008h
(pid1)
[8]
Forced duty-cycle select.
0: Use PID-computed duty cycle
1: Use pid_force_duty
pid
pid_osp_ff_thr
RW
7000_1C18h
(pid0)
7000_2018h
(pid1)
[6:0]
Defines the minimum PID FF value,
above which to begin checking for
an open-sense fault during soft-
start. This fault will indicate a
larger-than-expected impedance
between V
OUT
and V
OUT_sen
.
LSB = 2^-7, range = 0.0 to 0.9921875
pid
pid_osp_duty_thr
RW
7000_1C18h
(pid0)
7000_2018h
(pid1)
[13:7]
Defines the minimum PID duty
cycle value, above which to begin
checking for an open-sense fault
during soft-start. This fault will
indicate a larger-than-expected
impedance between V
OUT
and
V
OUT_sen
.
LSB = 2^-7, range = 0.0 to 0.9921875
pid
pid_osp_ff_scale
RW
7000_1C18h
(pid0)
7000_2018h
(pid1)
[17:14] Scale factor applied to PID FF term
to detect an open-sense fault
between V
OUT
and V
OUT_sen
during
soft-start. A setting of 0 will disable
this fault check.
LSB = 0.5, range = 0.0 to 7.5
pid
pid_ff_vrect_override
RW
7000_1C1Ch
(pid0)
[11:0]
V
RECT
override for PID FF
computation in internal VSADC
format (i.e., as sensed at VRSEN,
