Infineon XDPP1100, Technical Reference Manual

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User Manual 127 of 562 V 1.0
2021-08-25
XDPP1100 technical reference manual
Digital power controller
Digital pulse width modulator
Table 35 Typical settings of the register rampX_pid_sel
Topology ramp0_pid_sel ramp1_pid_sel
Single loop, single-phase 0 0
Single loop, interleaved 0 0
Dual loop 0 1
In order to generate the PWM pulses, the ramp generator produces the timing information based on a timing
ramp. This timing ramp consists of a digital counter which counts from t = 0 up to the maximum ramp count,
ramp_max, before returning to 0 and counting up again. The ramp counter functionality is illustrated in
Figure
55 .
Figure 55 Ramp counter for a) non-bridge and b) bridge topologies
The ramp counter operation depends on the topology:
•
For non-bridge topologies (buck, ACF, etc.) the ramp period is equal to the switching period (T
switch
) and
ramp_max is equal to a digital representation of T
switch
, as shown in the upper part of Figure 55 .
•
For bridge topologies (HB, FB) the ramp period equals half of the switching period (T
switch
/2) and ramp_max
equals a digital representation of T
switch
/2, as shown in the lower part of Figure 55 .
ramp count = 0
ramp count = ramp_max
t = 0 t = T
SWITCH
t = 2*T
SWITCH
t = 3*T
SWITCH
a) Ramp counting for non-bridge topologies
ramp count = 0
ramp count = ramp_max
t = 0 t = T
SWITCH
t = 2*T
SWITCH
t = 3*T
SWITCH
b) Ramp counting for bridge topologies
t = T
SWITCH
/2 t = 3*T
SWITCH
/2 t = 5*T
SWITCH
/2
even_cycle
odd_cycle