Infineon XDPP1100, Technical Reference Manual

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User Manual 364 of 562 V 1.0
2021-08-25
XDPP1100 technical reference manual
Digital power controller
Central processing unit subsystem
Register name Field name Access Address Bits Description
0: Status of “ bif_per_pmbus_clk ”
clock is not affected
1: Disable
“ bif_per_pmbus_clk ”
clock
CLK_EN_CTRL
_CLR bif_per_ssp_clk_g W 4000_2034h [14] Reserved
CLK_EN_CTRL
_CLR bif_per_i2c_clk_g W 4000_2034h [15] Disable the bif_per_i2c_clk clock.
0: Status of
“ bif_per_i2c_clk ” clock
is not affected
1: Disable
“ bif_per_i2c_clk ” clock
CLK_EN_CTRL
_CLR bif_per_uart_clk_g W 4000_2034h [16] Disable the bif_per_uart_clk clock.
0: Status of
“ bif_per_uart_clk ”
clock is not affected
1: Disable
“ bif_per_uart_clk ” clock
CLK_EN_CTRL
_CLR dtimer1_clk_g W 4000_2034h [17] Disable the dtimer1_clk clock.
0: Status of
“ dtimer1_clk ” clock is
not affected
1: Disable
“ dtimer1_clk ” clock
CLK_EN_CTRL
_CLR dtimer2_clk_g W 4000_2034h [18] Disable the dtimer2_clk clock.
0: Status of
“ dtimer2_clk ” clock is
not affected
1: Disable
“ dtimer2_clk ” clock
CLK_EN_CTRL
_CLR dtimer3_clk_g W 4000_2034h [19] Disable the dtimer3_clk clock.
0: Status of
“ dtimer3_clk ” clock is
not affected
1: Disable
“ dtimer3_clk ” clock
CLK_EN_CTRL
_CLR wdt_clk_g W 4000_2034h [20] Disable the wdt_clk clock.
0: Status of
“ wdt_clk ” clock is not
affected
1: Disable
“ wdt_clk ” clock
CLK_EN_CTRL
_CLR gpio0_clk_g W 4000_2034h [21] Disable the gpio0_clk clock.
0: Status of
“ gpio0_clk ” clock is not
affected
1: Disable
“ gpio0_clk ” clock
CLK_EN_CTRL
_CLR gpio1_clk_g W 4000_2034h [22] Disable the gpio1_clk clock.
0: Status of
“ gpio1_clk ” clock is not
affected
1: Disable
“ gpio1_clk ” clock
CLK_EN_CTRL
_CLR dtimer1_kernel_clk
_g W 4000_2034h [23] Disable the dtimer1_kernel_clk
clock.
0: Status of
“ dtimer1_kernel_clk ”
clock is not affected
1: Disable
“ dtimer1_kernel_clk ”
clock