User Manual 544 of 562 V 1.0
2021-08-25
XDPP1100 technical reference manual
Digital power controller
Central processing unit subsystem
Register name Field name
Access Address
Bits
Description
associated with the character at the
top of the FIFO.
UARTRSR_UAR
TECR
PE
RW
700C_0004h [1]
Parity error. When set to 1, it
indicates that the parity of the
received data character does not
match the parity that the EPS and
SPS bits in the line control register,
UARTLCR_H on page 31, select. This
bit is cleared to 0 by a write to
UARTECR. In FIFO mode, this error
is associated with the character at
the top of the FIFO.
UARTRSR_UAR
TECR
BE
RW
700C_0004h [2]
Break error. This bit is set to 1 if a
break condition was detected,
indicating that the received data
input was held low for longer than a
full-word transmission time
(defined as start, data, parity, and
stop bits). This bit is cleared to 0
after a write to UARTECR. In FIFO
mode, this error is associated with
the character at the top of the FIFO.
When a break occurs, only one 0
character is loaded into the FIFO.
The next character is only enabled
after the receive data input goes to
a 1 (marking state) and the next
valid start bit is received.
UARTRSR_UAR
TECR
OE
RW
700C_0004h [3]
Overrun error. This bit is set to 1 if
data is received and the FIFO is
already full. This bit is cleared to 0
by a write to UARTECR. The FIFO
contents remain valid because no
more data is written when the FIFO
is full; only the contents of the shift
register are overwritten. The CPU
must now read the data, to empty
the FIFO.
UARTFR
CTS
R
700C_0018h [0]
Clear to send. This bit is the
complement of the UART clear to
send, nUARTCTS, modem status
input. That is, the bit is 1 when
nUARTCTS is low.
UARTFR
DSR
R
700C_0018h [1]
Data set ready. This bit is the
complement of the UART data set
ready, nUARTDSR, modem status
input. That is, the bit is 1 when
nUARTDSR is low.
