User Manual
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V 1.0
2021-08-25
XDPP1100 technical reference manual
Digital power controller
Digital pulse width modulator
Peripheral Field name
Access Address
Bits
Description
pwm
pwm12_dr
RW
7000_2C80h [7:0]
PWM12 rising edge delay (dead)
time from t1 or t2. Mapping of the
rising edge to t1 or t2 defined by
pwm12_rise_sel. In order to
synchronously update all pwmX_dr
and pwmX_df times
simultaneously, an update to any
dead time register only becomes
effective after 7000_2C80h
(pwm12_dr, pwm12_df) is written.
Computed by FW from PMBus
command as follows:
pwm12_dr[7:0] =
PWM_DEADTIME[189:182]
LSB = 1.25 ns, range = 0.0 to
318.75 ns
pwm
pwm12_df
RW
7000_2C80h [15:8]
PWM12 falling edge delay (dead)
time from t1 or t2. Mapping of the
falling edge to t1 or t2 defined by
pwm12_fall_sel. In order to
synchronously update all dead
times simultaneously, an update to
any dead time register only
becomes effective after
7000_2C80h (pwm12_dr,
pwm12_df) is written.
Computed by FW from PMBus
command as follows:
pwm12_df[7:0] =
PWM_DEADTIME[181:176]
LSB = 1.25 ns, range = 0.0 to
318.75 ns
pwm
ramp0_dutyc_force_
status
R
7000_2C84h [0]
This register bit is set to 1 when a
new duty-cycle force has been
applied on ramp0. It is cleared to 0
when either ramp0_force_duty_en
or ramp0_force_duty changes.
pwm
ramp1_dutyc_force_
status
R
7000_2C84h [1]
This register bit is set to 1 when a
new duty-cycle force has been
applied on ramp1. It is cleared to 0
when either ramp1_force_duty_en
or ramp1_force_duty changes.
pwm
ramp0_t1_irq_sel
RW
7000_2C8Ch [2:0]
PWM ramp0 t1 IRQ source select.
0: t1 IRQ disabled
1: t1
2: t1 even
3: t1 odd
4 to 7: IRQ set by
ramp0_irq_phase[3:0]
