User Manual 329 of 562 V 1.0
2021-08-25
XDPP1100 technical reference manual
Digital power controller
Central processing unit subsystem
A DMA is available to handle autonomous data transfers, and to avoid BW losses on the microcontroller in case
of data movements.
AHB to APB Arm® bridges handle the protocol conversion between the two AMBA® layers.
The CPUS includes a memory management unit (MMU) that can remap memory addresses based on a
configurable scheme, allowing the implementation of a code-patching mechanism.
15.1
CPUS bus matrix
The CPUS bus matrix implements decoding and arbitration in order to route all master requests to slaves. The
bus matrix has two AHB slave ports, to which Cortex®-M0 and DMA AHB master ports are connected, and eight
AHB master ports, to which all the AHB slave peripherals are connected. Master
–
slave interconnections are
shown in
; while the Cortex®-M0 can access all the peripherals, the DMA has some limitations for
application stability purposes.
Table 88
Bus matrix internal interconnection
Master port
Peripheral
S0:
Cortex®-M0
S1:
DMA
M0
ROM/OTP
Yes
Yes
M1
RAM2
Yes
Yes
M2
RAM1
Yes
Yes
M3
CSC
Yes
No
M4
OTP CONF, DMA CONF
Yes
No
M5
WDT, DTIMER1/2/3, GPIO0/1
Yes
No
M6
BIF REGFILE (CONTROL)
Yes
Yes
M7
PMBus/CRC/I
2
C
Yes
Yes
15.2
Cortex®-M0 CPU
The Cortex®-M0 processor is a 32-bit reduced instruction set computing (RISC) processor with a von Neumann
architecture (single-bus interface).
It uses an instruction set defined in the ARMv6 architecture with Thumb and Thumb-2 support. Thumb-2
technology extended the previous Thumb instruction set to allow all operations to be carried out in one CPU
state. The instruction set in Thumb-2 included both 16-bit and 32-bit instructions; most instructions generated
by the C compiler use the 16-bit instructions, and the 32-bit instructions are used when the 16-bit version
cannot carry out the required operations. This results in high code density and avoids the overhead of
switching between two instruction sets. In total, the Cortex®-M0 processor supports 56 base instructions. The
Cortex®-M0 processor is highly capable because the Thumb instruction set is highly optimized.
Academically, the Cortex®-M0 processor is classified as load-store architecture, as it has separate instructions
for reading and writing to memory, and instructions for arithmetic or logical operations that use registers.
The specification of the Cortex®-M0 are outlined in a number of Arm® documents. The Cortex®-M0 Devices
Generic User Guide covers the programmer’s model, instruction set
and general information about the
architecture. The full details of the instruction set,
programmer’s model and other topics are specifie
d in a
document called the ARMv6-M Architecture Reference Manual. The timing information of the processor core,
and implementation-related information are described in a document called the Cortex®-M0 Technical
