User Manual
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V 1.0
2021-08-25
XDPP1100 technical reference manual
Digital power controller
Digital pulse width modulator
Peripheral Field name
Access Address
Bits
Description
pwm
compensation_slope RW
7000_2C00h [19:18]
Defines the compensation ramp
slope when PCMC selected as
modulation type by
mode_control_loop0 or
mode_control_loop1. This single
register applies to both loops in the
case of a dual-loop system.
0: V
OUT
/L
1: V
OUT
/2L
2: V
OUT
/4L
3: Reserved
pwm
pwm1_fall_sel
RW
7000_2C04h [2:0]
Topology-driven PWM1 falling edge
select. t1 and t2 refer to the
modulated edges created by the
ramp. When using TE modulation,
t1 is fixed at time 0 and t2 is
modulated. When using LE
modulation, t2 is fixed at T
switch
(or
0.5 * T
switch
and T
switch
for bridge
topologies) and t1 is modulated.
When using dual-edge modulation,
t1 and t2 are centered around 0.5 *
T
switch
(or 0.25 * T
switch
and 0.75 *
T
switch
for bridge topologies) and
both are modulated. Odd and even
cycle designations are for use with
bridge topologies to distinguish
between half-cycles.
0: t1
1: t2
2: t1 even cycle
3: t2 even cycle
4: t1 odd cycle
5: t2 odd cycle
6: t1 delay
7: t2 delay
pwm
pwm1_rise_sel
RW
7000_2C04h [6:3]
Topology-driven PWM1 rising edge
select. t1 and t2 refer to the
modulated edges created by the
ramp. When using TE modulation,
t1 is fixed at time 0 and t2 is
modulated. When LE modulation,
t2 is fixed at T
switch
(or 0.5 * T
switch
and
T
switch
for bridge topologies) and t1
is modulated. When using dual-
edge modulation, t1 and t2 are
centered around 0.5 * T
switch
(or 0.25
* T
switch
and 0.75 * T
switch
for bridge
topologies) and both are
modulated. Odd and even cycle
