Infineon XDPP1100, Technical Reference Manual

Page: 370 / 562

User Manual 370 of 562 V 1.0
2021-08-25
XDPP1100 technical reference manual
Digital power controller
Central processing unit subsystem
Register name Field name Access Address Bits Description
0: Clock “ bif_reg_clk ” sleep state
clock gating status unchanged
1: Disable clock
“ bif_reg_clk ” sleep
state clock gating
CLK_SLEEP_M
SK_CNFG_CLR se_bif_per_svid_clk
_g W 4000_203Ch [12] Disable bif_per_svid_clk clock
gating when the Cortex®-M0 enters
sleep state. Note: The CRC32
peripheral is using the SVID slot so
this actually controls the CRC32
clock.
0: Clock
“ bif_per_svid_clk ” sleep
state clock gating status
unchanged
1: Disable clock
“ bif_per_svid_clk ”
sleep state clock gating
CLK_SLEEP_M
SK_CNFG_CLR se_bif_per_pmbus_
clk_g W 4000_203Ch [13] Disable bif_per_pmbus_clk clock
gating when the Cortex®-M0 enters
sleep state.
0: Clock
“ bif_per_pmbus_clk ” sleep
state clock gating status
unchanged
1: Disable clock
“ bif_per_pmbus_clk ” sleep state
clock gating
CLK_SLEEP_M
SK_CNFG_CLR se_bif_per_ssp_clk
_g W 4000_203Ch [14] Reserved
CLK_SLEEP_M
SK_CNFG_CLR se_bif_per_i2c_clk_
g W 4000_203Ch [15] Disable bif_per_i2c_clk clock gating
when the Cortex®-M0 enters sleep
state.
0: Clock
“ bif_per_i2c_clk ” sleep
state clock gating status
unchanged
1: Disable clock
“ bif_per_i2c_clk ”
sleep state clock gating
CLK_SLEEP_M
SK_CNFG_CLR se_bif_per_uart_clk
_g W 4000_203Ch [16] Disable bif_per_uart_clk clock
gating when the Cortex®-M0 enters
sleep state.
0: Clock
“ bif_per_uart_clk ” sleep
state clock gating status
unchanged
1: Disable clock
“ bif_per_uart_clk ”
sleep state clock gating
CLK_SLEEP_M
SK_CNFG_CLR se_dtimer1_clk_g W 4000_203Ch [17] Disable dtimer1_clk clock gating
when the Cortex®-M0 enters sleep
state.