User Manual 545 of 562 V 1.0
2021-08-25
XDPP1100 technical reference manual
Digital power controller
Central processing unit subsystem
Register name Field name
Access Address
Bits
Description
UARTFR
DCD
R
700C_0018h [2]
Data carrier detect. This bit is the
complement of the UART data
carrier detect, nUARTDCD, modem
status input. That is, the bit is 1
when nUARTDCD is low.
UARTFR
BUSY
R
700C_0018h [3]
UART busy. If this bit is set to 1, the
UART is busy transmitting data.
This bit remains set until the
complete byte, including all the
stop bits, has been sent from the
shift register. This bit is set as soon
as the transmit FIFO becomes non-
empty, regardless of whether the
UART is enabled or not.
UARTFR
RXFE
R
700C_0018h [4]
Receive FIFO empty. The meaning
of this bit depends on the state of
the FEN bit in the line control
register, UARTLCR_H. If the FIFO is
disabled, this bit is set when the
receive holding register is empty. If
the FIFO is enabled, the RXFE bit is
set when the receive FIFO is empty.
UARTFR
TXFF
R
700C_0018h [5]
Transmit FIFO full. The meaning of
this bit depends on the state of the
FEN bit in the line control register,
UARTLCR_H. If the FIFO is disabled,
this bit is set when the transmit
holding register is full. If the FIFO is
enabled, the TXFF bit is set when
the transmit FIFO is full.
UARTFR
RXFF
R
700C_0018h [6]
Receive FIFO full. The meaning of
this bit depends on the state of the
FEN bit in the line control register,
UARTLCR_H. If the FIFO is disabled,
this bit is set when the receive
holding register is full. If the FIFO is
enabled, the RXFF bit is set when
the receive FIFO is full.
UARTFR
TXFE
R
700C_0018h [7]
Transmit FIFO empty. The meaning
of this bit depends on the state of
the FEN bit in the line control
register, UARTLCR_H on page 31. If
the FIFO is disabled, this bit is set
when the transmit holding register
is empty. If the FIFO is enabled, the
TXFE bit is set when the transmit
FIFO is empty. This bit does not
