User Manual
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V 1.0
2021-08-25
XDPP1100 technical reference manual
Digital power controller
Compensator
Both the duty cycle and FF must be above their corresponding thresholds,
pid_osp_duty_thr
and
pid_osp_ff_thr
, in order to prevent false fault detection at low voltages during start-up, when duty cycle is
much larger than the FF (e.g., at V
OUT
= 0 V). The region where the fault is declared is emphasized in blue in
. This OSP fault region is formed assuming the minimum duty cycle limit of 0.3 and the minimum FF
threshold of 0.05 and a scaling factor of 3.0.
Figure 53
PID-based open VS detection
6.5
Compensation filter registers
The relevant compensator-related registers and their descriptions are provided in
Table 34
Compensator-related register descriptions
Peripheral Field name
Access Address
Bits
Description
vsen
vsp_verrn_clamp_thresh RW
7000_0800h
(VSEN)
7000_1000h
(BVSEN)
[2:0]
V
errn
clamp threshold at PID input
where V
errn
is defined as the control
voltage minus the sensed V
OUT
.
Ignoring droop,
V
errn
=
OSP fault
region
0.2
0.4
0.6
0.8
1.0
0.2
0.4
0.6
0.8
1.0
FF = V
CONTROL
/ V
RECT
PI
D
du
ty
cyc
le
o
ut
pu
t
pid_osp_duty_thr = 0.3
pid_osp_ff_thr = 0.05
