User Manual 476 of 562 V 1.0
2021-08-25
XDPP1100 technical reference manual
Digital power controller
Central processing unit subsystem
Register name Field name
Access Address
Bits
Description
1: Register reports the latest illegal
address causing a fault
MMU_ERR_RP
T_CLR
CLR
W
4000_4708h [0]
Write-only register that clears
MMU_ERR_RPT.
15.6
DMA controller
The DMA controller is an Arm® PrimeCell IP (PL230); extensive documentation can be found in the
“A
rm®
PrimeCell µ
DMA controller (PL230) Technical Reference Manual”.
The principal features of the DMA controller are:
•
It is compatible with AHB-Lite for DMA transfers
•
It is compatible with APB for programming the registers
•
It has a single AHB-Lite master for transferring data using a 32-bit address bus and 32-bit data bus
•
It has a configurable number of DMA channels
•
Each DMA channel has dedicated handshake signals
•
Each DMA channel has a programmable priority level
•
Each priority level arbitrates using a fixed priority that is determined by the DMA channel number
•
It supports multiple transfer types:
o
memory-to-memory
o
memory-to-peripheral
o
peripheral-to-memory
•
It supports multiple DMA cycle types
•
It supports multiple DMA transfer data widths
•
Each DMA channel can access a primary, and alternate, channel control data structure
•
All the channel control data is stored in system memory (RAM) in little-endian format
•
It performs all DMA transfers using the single AHB-Lite burst type
•
The destination data width is equal to the source data width
•
The number of transfers in a single DMA cycle can be programmed from 1 to 1024
•
The transfer address increment can be greater than the data width
