Infineon XDPP1100, Technical Reference Manual

Page: 117 / 562

User Manual 117 of 562 V 1.0
2021-08-25
XDPP1100 technical reference manual
Digital power controller
Compensator
6.3 Control mode selection – peak current mode
This section describes the selection of control mode in more detail, focusing on the compensator-related
register settings for PCMC. However, most PCMC-related circuitry and detailed functionality is discussed in the
PWM chapter that follows.
The control mode for the compensator can be selected via registers mode_control_loop0 ,
mode_control_loop1 , for Loop 0 and Loop 1 respectively. The control mode options are:
•
VMC
•
PCMC on secondary
•
PCMC on primary
The difference between these control methods is that for VMC, the compensator output is directly the duty
cycle, whereas for the PCMC the compensator output is a reference current that is compared to the sensed
current. Therefore, depending on the desired control method, the compensator output format varies:
•
In VMC the compensator output is clamped to the unsigned range 0.0 to 1.0
•
I n PCMC the compensator output is “normalized reference current” where the normalization is within the
IADC maximum range, leading to a signed output range -1.0 to +1.0
The inherent nature of current mode control provides simple dynamics, and therefore, typically for PCMC a
Type II compensator is sufficient. The difference between Type II and III compensators is that Type II consists of
PI and a single-pole, whereas Type III is PID with two poles. The compensator in
Figure 45 provides a Type III
response, and in order to obtain the Type II response for PCMC the following need to be considered:
•
The compensator includes two single-pole LPFs but neither of them is possible to bypass. However, by
setting one of the filter coefficients via register
pid_kfp1_index_1ph or pid_kfp2_index_1ph to maximum
BW, the Type II response can be approximated.
•
Due to the exponential nature of the PID coefficients, setting register pid_kd_index_1ph to zero does not
result in a zero-valued K
D
. However, when PCMC mode is selected (register mode_control_loop0/1) it is
possible to override the exponential setting and force K
D
to be zero via register pid_kd_index_1ph . If a non-
zero K
D
is desired in PCMC, it can be set via pid_kd_index_1ph to a non-zero setting.
The FF is automatically set to 0 when a loop is configured for PCMC mode and input voltage-based PID
coefficient adjustment is automatically disabled.
6.4 Open sense fault detection
The feedback loop is broken if the external resistor divider is not properly placed. The compensator is capable
of detecting a missing sense resistor within the external resistor divider, between the output voltage and VSEN
(BVSEN) (
Figure 2 ). The fault detection is based on searching for duty-cycle value which is larger than the FF
term. The following settings can be defined for the fault detection:
•
Register pid_osp_duty_thr defines the minimum duty cycle (i.e., compensator output) at which to begin
looking for a fault.
•
Register pid_osp_ff_thr defines the minimum PID FF value at which to begin looking for a fault.
•
Register pid_osp_ff_scale defines how much greater the duty must be than the FF to declare a fault.
Equation (6.33) shows the condition for a fault declaration.
𝑑𝑢𝑡𝑦 > 𝑝𝑖𝑑_𝑜𝑠𝑝_𝑓𝑓_𝑠𝑐𝑎𝑙𝑒 ∗ 𝐹𝐹
(6.33)