User Manual 397 of 562 V 1.0
2021-08-25
XDPP1100 technical reference manual
Digital power controller
Central processing unit subsystem
OTP timing requirements are specified in
Table 100
OTP timing requirements
Timing
Description
Requirement [ns]
t
RAS
READ address setup time
4.4
t
RAH
READ address hold-time
1.0
t
RP
READ pulse width
37
t
RR
READ recovery time
14.8
t
RACC
READ access time
11.2
On the AHB side, once a read request is initiated, it takes seven H
CLK
cycles to complete an access; AHB FSM
holds H
READY
low (inserting wait cycles on the bus) until the OTP macro READ completion, then address
consecutive accesses have zero wait state up to the following three reads (if the first address was 128-bit
aligned); an access to a different OTP word again triggers a seven-cycle wait state.
The OTP module implements a prefetch FSM to mitigate the penalties on the access time. After any access,
prefetch FSM automatically starts a read on the following OTP word, caching 128-bit data that correspond to
the following four AHB 32-bit words.
The prefetching feature is enabled by default, but can be statically disabled by setting the DIS_PF field on the
CONF register to high.
Prefetch FSM access time is the same as AHB FSM (seven cycles), but as it is running while AHB is still
consuming the main access data, it enables saving some cycles on a hit (access to consecutive addresses, see
Figure 109
Access to two OTP 128-bit consecutive words
When accessing two consecutive words, four wait state cycles are saved on the AHB bus thanks to the
prefetching. This improvement is less if the starting address is not aligned on 128 bits, or if not all of the data of
the first read is used (there is less time available for the prefetch unit to complete its read).
