Infineon XDPP1100, Technical Reference Manual

Page: 367 / 562

User Manual 367 of 562 V 1.0
2021-08-25
XDPP1100 technical reference manual
Digital power controller
Central processing unit subsystem
Register name Field name Access Address Bits Description
peripheral is using the SVID slot so
this actually controls the CRC32
clock.
0: Clock
“ bif_per_svid_clk ” sleep
state clock gating status
unchanged
1: Enable clock
“ bif_per_svid_clk ”
sleep state clock gating
CLK_SLEEP_M
SK_CNFG_SET se_bif_per_pmbus_
clk_g W 4000_2038h [13] Enable bif_per_pmbus_clk clock
gating when the Cortex®-M0 enters
sleep state.
0: Clock
“ bif_per_pmbus_clk ” sleep
state clock gating status
unchanged
1: Enable clock
“ bif_per_pmbus_clk ” sleep state
clock gating
CLK_SLEEP_M
SK_CNFG_SET se_bif_per_ssp_clk
_g W 4000_2038h [14] Reserved
CLK_SLEEP_M
SK_CNFG_SET se_bif_per_i2c_clk_
g W 4000_2038h [15] Enable bif_per_i2c_clk clock gating
when the Cortex®-M0 enters sleep
state.
0: Clock
“ bif_per_i2c_clk ” sleep
state clock gating status
unchanged
1: Enable clock
“ bif_per_i2c_clk ”
sleep state clock gating
CLK_SLEEP_M
SK_CNFG_SET se_bif_per_uart_clk
_g W 4000_2038h [16] Enable bif_per_uart_clk clock
gating when the Cortex®-M0 enters
sleep state.
0: Clock
“ bif_per_uart_clk ” sleep
state clock gating status
unchanged
1: Enable clock
“ bif_per_uart_clk ”
sleep state clock gating
CLK_SLEEP_M
SK_CNFG_SET se_dtimer1_clk_g W 4000_2038h [17] Enable dtimer1_clk clock gating
when the Cortex®-M0 enters sleep
state.
0: Clock
“ dtimer1_clk ” sleep state
clock gating status unchanged
1: Enable clock
“ dtimer1_clk ” sleep
state clock gating
CLK_SLEEP_M
SK_CNFG_SET se_dtimer2_clk_g W 4000_2038h [18] Enable dtimer2_clk clock gating
when the Cortex®-M0 enters sleep
state.