User Manual 486 of 562 V 1.0
2021-08-25
XDPP1100 technical reference manual
Digital power controller
Central processing unit subsystem
Register name Field name
Access Address
Bits
Description
In order to write to GPIODATA, the
corresponding bits in the mask,
resulting from the address bus
PADDR[9:2], must be high.
Otherwise, the bit values remain
unchanged by the write.
Similarly, the values read from this
register are determined for each bit
by the mask bit derived from the
address used to access the data
register, PADDR[9:2]. Bits that are 1
in the address mask cause the
corresponding bits in GPIODATA to
be read, and bits that are 0 in the
address mask cause the
corresponding bits in GPIODATA to
be read as 0, regardless of their
value.
A read from GPIODATA returns the
last bit value written if the
respective pins are configured as
output, or it returns the value on
the corresponding input GPIN bit
when these are configured as
inputs. All bits are cleared by a
reset.
GPIODIR
DIR
RW
6004_0400h
6005_0400h
[7:0]
The GPIODIR register is the data
direction register. Bits set to high in
the GPIODIR configure the
corresponding pin to be an output.
Clearing a bit configures the pin to
be input. All bits are cleared by a
reset. Therefore, the GPIO pins are
input by default.
For each bit [x]:
0: GPIOx configured as input
1: GPIOx configured as output
GPIOIS
INTSENSE
RW
6004_0404h
6005_0404h
[7:0]
The GPIOIS register is the interrupt
sense register. Bits set to high in
GPIOIS configure the
corresponding pins to detect levels.
Clearing a bit configures the pin to
detect edges. All bits are cleared by
a reset.
For each bit [x]:
0: GPIOx is edge sensitive
1: GPIOx is level sensitive
