User Manual 511 of 562 V 1.0
2021-08-25
XDPP1100 technical reference manual
Digital power controller
Central processing unit subsystem
Register name Field name
Access Address
Bits
Description
0: CPU is in charge to generate
ACK/NACK
1: HW takes care of generation of
ACK/NACK. HW must be properly
programmed.
CNFG
EN_AUTO_TRANSM
IT_TX_PEC
RW
7008_0004h [5]
Enable/Disable automatic transfer
of the TX PEC.
0: CPU is in charge of providing the
TX PEC to be transmitted
1: HW takes care of transmission of
the TX PEC as soon as the
byte_cnt_tx is equal to the
programmed byte_to_tx
CNFG
USE_START_IRQ_D
ELAY
RW
7008_0004h [6]
Enable/Disable usage of delayed
START_IRQ. Enable/Disable the
FSM of PMBus to screen out the
transactions not belonging to the
device; the screen-out will take
place only on first start after stop
and not for restart.
0: START_IRQ interrupt always
occurs at the start phase, then the
CPU is in charge of evaluating all of
the PMBus transactions
1: START_IRQ interrupt is delayed
at the end of reception of the
PMBus address, before the
direction bit, to allow PMBus
transaction screening
CNFG
DEBOUNCE_LENGT
H
RW
7008_0004h [9:7]
Configure the number of
consecutive bif_pmbus_kernel_clk
cycles to accept a status change on
scl_in and sda_in signals.
0: Signal must be stable for at least
one clock signal
1: Signal must be stable for at least
two clock signals
2: Signal must be stable for at least
three clock signals
3: Signal must be stable for at least
four clock signals
4: Signal must be stable for at least
five clock signals
5: Signal must be stable for at least
six clock signals
