Infineon XDPP1100, Technical Reference Manual

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User Manual 375 of 562 V 1.0
2021-08-25
XDPP1100 technical reference manual
Digital power controller
Central processing unit subsystem
Register name Field name Access Address Bits Description
0: Clock “ wdt_clk ” deep sleep state
clock gating status unchanged
1: Enable clock
“ wdt_clk ” deep
sleep state clock gating
CLK_DEEP_SL
EEP_MSK_CNF
G_SET dse_gpio0_clk_g W 4000_2040h [21] Enable gpio2_clk clock gating when
the Cortex®-M0 enters deep sleep
state.
0: Clock
“ gpio2_clk ” deep sleep
state clock gating status
unchanged
1: Enable clock
“ gpio2_clk ” deep
sleep state clock gating
CLK_DEEP_SL
EEP_MSK_CNF
G_SET dse_gpio1_clk_g W 4000_2040h [22] Enable gpio1_clk clock gating when
the Cortex®-M0 enters deep sleep
state.
0: Clock
“ gpio1_clk ” deep sleep
state clock gating status
unchanged
1: Enable clock
“ gpio1_clk ” deep
sleep state clock gating
CLK_DEEP_SL
EEP_MSK_CNF
G_CLR dse_hosc_clk_g W 4000_2044h [0] Disable hosc_clk clock gating when
Cortex®-M0 will enter the deep
sleep state, if the hosc_clk clock
gating control has been enabled.
Warning: Only external reset
assertion can remove clock gating if
no external wakeup source has
been enabled before.
0: Clock
“ hosc_clk ” deep sleep
state clock gating status
unchanged
1: Disable clock
“ hosc_clk ” deep
sleep state gating
CLK_DEEP_SL
EEP_MSK_CNF
G_CLR dse_rom_clk_g W 4000_2044h [1] Disable rom_clk clock gating when
the Cortex®-M0 enters deep sleep
state.
0: Clock
“ rom_clk ” deep sleep state
clock gating status unchanged
1: Disable clock
“ rom_clk ” deep
sleep state clock gating
CLK_DEEP_SL
EEP_MSK_CNF
G_CLR dse_ram1_clk_g W 4000_2044h [2] Disable ram1_clk clock gating when
the Cortex®-M0 enters deep sleep
state.
0: Clock
“ ram1_clk ” deep sleep
state clock gating status
unchanged