Infineon XDPP1100, Technical Reference Manual

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User Manual 241 of 562 V 1.0
2021-08-25
XDPP1100 technical reference manual
Digital power controller
Fault handler
9.1.11 Loop fault latching
The loop fault latching submodule is responsible for registering and holding the occurrence of loop faults for
use by the shutdown submodule and reporting to the FW. As was shown in
Figure 77 , the outputs from the fault
detection submodules are gathered together to form the fault_loop_bus signal, which is the data input to the
loop fault latching submodule. A block diagram of the loop fault latching function is shown in
Figure 78 .
Figure 78 Loop fault latching block diagram
Several registers are provided to allow the FW to control if and how the loop faults are reported on
fault_reg_loop and fault_status_loop . These registers are:
•
fault_enable_loop , programmed via PMBus command FW_CONFIG_FAULTS bits [103:72], enables
individual faults for reporting on fault_reg_loop and fault_status_loop
•
fault_polarity_loop controls the polarity, active high or low, of individual faults reported on
fault_reg_loop and fault_status_loop
•
fault_force_loop is bitwise ORed with fault_loop_bus to provide a method for FW to trigger the HW-based
loop faults
•
fault_clear_loop allows individual faults to be cleared on fault_reg_loop and fault_status_loop
•
fault_block_on_shut prevents additional fault reporting after an initial shutdown fault has occurred
Table 64 shows the shared bit-to-fault mapping that applies to registers:
•
fault_enable_loop
•
fault_polarity_loop
•
fault_force_loop
•
fault_clear_loop
•
fault_reg_loop
•
fault_status_loop
Table 64 Bit mapping of loop faults
Bit Fault Bit Fault
[0] Reserved [12] IOUT_UC_FAULT
[1] VOUT_OV_FAULT [13] MFR_IOUT_OC_FAST_FAULT
[2] VOUT_OV_WARN [14] IIN_OC_FAULT
[3] VOUT_UV_FAULT [15] IIN_OC_WARN
[4] VOUT_UV_WARN [16] OT_FAULT
[5] VIN_OV_FAULT [17] OT_WARN
[6] VIN_OV_WARN [18] UT_FAULT
[7] VIN_UV_FAULT [19] UT_WARN
fault_loop_bus[31:0]
fault_clear_loop[31:0]
fault_enable_loop[31:0]
fault_force_loop[31:0]
fault_polarity_loop[31:0]
fault_reg_loop[31:0]
fault_status_loop[31:0]
fault_loop_in[31:0]
50 MHz
2 MHz
[31:0]
[31:0] [31:0]
[31:0] [31:0]
Note: set has priority over reset on SR flip-flops
fault_block_on_shut
fault_shut_irq
block_fault_update
D
Q
Q
SET
CLR
R
D
Q
Q
SET
CLR
R