User Manual
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V 1.0
2021-08-25
XDPP1100 technical reference manual
Digital power controller
Digital pulse width modulator
Peripheral Field name
Access Address
Bits
Description
pwm
ramp0_force_t2_en
RW
7000_2C3Ch [11]
PWM ramp0 t2 force enable.
0: t2 determined by modulation
scheme and duty cycle
1: t2 set by ramp0_force_t2
pwm
tswitch1
RW
7000_2C40h [8:0]
PWM ramp1 switching period. This
register defines the switching
period of ramp1 when ramp1 is not
synced to an external sync signal.
Computed by FW from PMBus
command as follows:
T
switch1
= 1/
(FREQUENCY_SWITCH(Hz) * 20ns)
LSB = 20 ns, range = 0.0 to 10.22 µs
pwm
ramp1_dc_max
RW
7000_2C44h [7:0]
PWM ramp1 max. duty cycle (fixed).
See ramp1_dc_max_nom
description for scaled max. duty-
cycle information.
Computed by FW from PMBus
command as follows:
ramp1_dc_max = MAX_DUTY
LSB = 0.5 percent, range = 0.0 to
99.5 percent
pwm
ramp1_pw_min
RW
7000_2C44h [15:8]
PWM ramp1 min. pulse width.
When the duty cycle from the PID is
less than this value the duty-cycle
input to the ramp is either clamped
to this value or set to 0 as
determined by the setting of
ramp0_pw_min_state.
Computed by FW from PMBus
command as follows:
ramp1_pw_min = MFR_MIN_PW
LSB = 5 ns, range = 0 to 1275 ns
pwm
ramp1_force_duty
RW
7000_2C48h [7:0]
This forced duty-cycle value
overrides the ramp1 duty-cycle
input when selected by
ramp1_force_duty_en. Since this
force is applied at the ramp input,
upstream adjustments to the duty
cycle such as current balance in an
interleaved (multiphase) design are
overwritten. To not override the
current balance adjustment, use
pid_force_duty, which is applied
prior to the current balance
adjustments.
LSB = 0.3906 percent, range = 0.0 to
99.6094 percent
