User Manual 546 of 562 V 1.0
2021-08-25
XDPP1100 technical reference manual
Digital power controller
Central processing unit subsystem
Register name Field name
Access Address
Bits
Description
indicate if there is data in the
transmit shift register.
UARTFR
RI
R
700C_0018h [8]
Ring indicator. This bit is the
complement of the UART ring
indicator, nUARTRI, modem status
input. That is, the bit is 1 when
nUARTRI is low.
UARTILPR
ILPDVSR
RW
700C_0020h [7:0]
The UARTILPR register is the IrDA
low-power counter register. This is
an 8-bit read/write register that
stores the low-power counter
divisor value used to generate the
IrLPBaud16 signal by dividing down
UARTCLK.
The IrLPBaud16 signal is generated
by dividing down the UARTCLK
signal according to the low-power
divisor value written to the
UARTILPR register.
The low-power divisor value is
calculated as follows:
Low-power divisor (ILPDVSR) =
(FUARTCLK / FIrLPBaud16)
where FIrLPBaud16 is nominally
1.8432 MHz.
You must select the divisor so that
1.42 MHz less than FIrLPBaud16
less than 2.12 MHz results in a low-
power pulse duration of 1.41 to 2.11
µs (three times the period of
IrLPBaud16).
UARTIBRD
BAUD_DIVINT
RW
700C_0024h [15:0]
The UARTIBRD register is the
integer part of the baud rate divisor
value.
UARTFBRD
BAUD_DIVFRAC
RW
700C_0028h [5:0]
The UARTFBRD register is the
fractional part of the baud rate
divisor value.
The baud rate divisor is calculated
as follows:
Baud rate divisor BAUDDIV =
(FUARTCLK/(16 × baud rate))
where FUARTCLK is the UART
reference clock frequency.
The BAUDDIV is comprised of the
integer value (BAUD_DIVINT) and
the fractional value (BAUD
_DIVFRAC).
