Infineon XDPP1100, Technical Reference Manual

Page: 373 / 562

User Manual 373 of 562 V 1.0
2021-08-25
XDPP1100 technical reference manual
Digital power controller
Central processing unit subsystem
Register name Field name Access Address Bits Description
CLK_DEEP_SL
EEP_MSK_CNF
G_SET dse_cnfg_otp1_w_c
lk_g W 4000_2040h [6] Enable cnfg_otp1_w_clk clock
gating when the Cortex®-M0 enters
deep sleep state.
0: Clock
“ cnfg_otp1_w_clk ” deep
sleep state clock gating status
unchanged
1: Enable clock
“ cnfg_otp1_w_clk ”
deep sleep state clock gating
CLK_DEEP_SL
EEP_MSK_CNF
G_SET dse_cnfg_dma_clk_
g W 4000_2040h [10] Enable cnfg_dma_clk clock gating
when the Cortex®-M0 enters deep
sleep state.
0: Clock
“ cnfg_dma_clk ” deep sleep
state clock gating status
unchanged
1: Enable clock
“ cnfg_dma_clk ”
deep sleep state clock gating
CLK_DEEP_SL
EEP_MSK_CNF
G_SET dse_bif_reg_clk_g W 4000_2040h [11] Enable bif_reg_clk clock gating
when the Cortex®-M0 enters deep
sleep state.
0: Clock
“ bif_reg_clk ” deep sleep
state clock gating status
unchanged
1: Enable clock
“ bif_reg_clk ” deep
sleep state clock gating
CLK_DEEP_SL
EEP_MSK_CNF
G_SET dse_bif_per_svid_cl
k_g W 4000_2040h [12] Enable bif_per_svid_clk clock
gating when the Cortex®-M0 enters
deep sleep state. Note: The CRC32
peripheral is using the SVID slot so
this actually controls the CRC32
clock.
0: Clock
“ bif_per_svid_clk ” deep
sleep state clock gating status
unchanged
1: Enable clock
“ bif_per_svid_clk ”
deep sleep state clock gating
CLK_DEEP_SL
EEP_MSK_CNF
G_SET dse_bif_per_pmbus
_clk_g W 4000_2040h [13] Enable bif_per_pmbus_clk clock
gating when the Cortex®-M0 enters
deep sleep state.
0: Clock
“ bif_per_pmbus_clk ” deep
sleep state clock gating status
unchanged
1: Enable clock
“ bif_per_pmbus_clk ” deep sleep
state clock gating