User Manual 483 of 562 V 1.0
2021-08-25
XDPP1100 technical reference manual
Digital power controller
Central processing unit subsystem
Register name Field name
Access Address
Bits
Description
0: No effect. Use the
CHNL_PRI_ALT_CLR Register to set
bit [x] to 0.
1: Selects the alternate data
structure for channel x
DMA_CHNL_P
RI_ALT_CLR
CHNL_PRI_ALT_CL
R
W
5000_0034h [15:0]
This register enables you to
configure a DMA channel to use the
primary data structure.
For each bit [x]:
0: No effect. Use the
CHNL_PRI_ALT_SET Register to
select the alternate data structure.
1: Selects the primary data
structure for channel x
DMA_CHNL_P
RIORITY_SET
CHNL_PRIORITY_SE
T
RW
5000_0038h [15:0]
This register enables you to
configure a DMA channel to use the
high priority level. Reading the
register returns the status of the
channel priority mask.
For each bit [x],
On READ:
0: DMA channel x is using the
default priority level
1: DMA channel x is using a high
priority level
On WRITE:
0: No effect. Use the
CHNL_ENABLE_CLR Register to set
channel x to the default priority
level.
1: Channel x uses the high priority
level
DMA_CHNL_P
RIORITY_CLR
CHNL_PRIORITY_CL
R
W
5000_003Ch [15:0]
This write-only register enables you
to configure a DMA channel to use
the default priority level.
For each bit [x]:
0: No effect. Use the
CHNL_ENABLE_SET Register to set
channel x to the high priority level.
1: Channel x uses the default
priority level
DMA_ERR_CLR ERR_CLR
RW
5000_004Ch [0]
The read/write ERR_CLR register
returns the status of dma_err, and
enables you to set dma_err low.
On READ:
