User Manual
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V 1.0
2021-08-25
XDPP1100 technical reference manual
Digital power controller
Digital pulse width modulator
Peripheral Field name
Access Address
Bits
Description
pwm
ramp1_phase
RW
7000_2C20h [7:0]
ramp1 phase alignment with
respect to sync signal selected with
ramp1_sync_sel.
Computed by FW from PMBus
command as follows:
ramp1_phase = 2^8 *
PAGE1.INTERLEAVE[3:0]/
PAGE1.INTERLEAVE[7:4]
LSB = 1.40625 degrees, range = 0.0
to 358.59375 degrees
pwm
pwm_force_hi
RW
7000_2C24h [11:0]
Force PWM output high, [0]
corresponds to PWM1, [11]
corresponds to PWM12. This
register has lower priority than
pwm_force_lo.
pwm
pwm_force_lo
RW
7000_2C24h [23:12]
Force PWM output low, [0]
corresponds to PWM1, [11]
corresponds to PWM12. This
register has higher priority than
pwm_force_hi.
pwm
pwm_on
7000_2C28h [11:0]
PWM channel enabled for pulse
generation when corresponding bit
position high, [0] corresponds to
PWM1, [11] corresponds to PWM12.
Note:
Intended to be driven by FW only.
pwm
tswitch0
RW
7000_2C2Ch [8:0]
PWM ramp0 switching period. This
register defines the switching
period of ramp0 when ramp0 is not
synced to an external sync signal.
Computed by FW from PMBus
command as follows:
T
switch0
= 1/
(FREQUENCY_SWITCH(Hz) * 20 ns)
LSB = 20 ns, range = 0.0 to 10.22 µs
pwm
ramp0_dc_max
RW
7000_2C30h [7:0]
PWM ramp0 max. duty cycle (fixed).
See ramp0_dc_max_nom
description for scaled max. duty
cycle information.
Computed by FW from PMBus
command as follows:
ramp0_dc_max = MAX_DUTY
LSB = 0.5 percent, range = 0.0 to
99.5 percent
pwm
ramp0_pw_min
RW
7000_2C30h [15:8]
PWM ramp0 min. pulse width.
When the duty cycle from the PID is
less than this value the duty cycle
input to the ramp is either clamped
to this value or set to 0 as
