User Manual
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V 1.0
2021-08-25
XDPP1100 technical reference manual
Digital power controller
Digital pulse width modulator
Figure 60
Functional block diagram of VMC
In VMC the compensator output, pid_duty, is directly interpreted as the duty cycle with a range of 0.0 to 0.9999.
In addition, two other sources contribute to the final duty cycle used to compute the PWM pulse width (PW).
These sources are as follows:
•
Current balance duty-cycle adjustment (ibal_duty_adj). This signal comes from the current balance function
(which will be described in
). It corrects for difference in the phase current in a dual-phase
(interleave) loop and it is applied only to ramp0. This is because the phase associated with ISEN contains the
current balance duty-cycle adjustment while the phase associated with BISEN does not.
•
Flux balance duty-cycle adjustment (fbal_duty_adj). This signal comes from the flux balance function (which
will be described in
). It corrects for the transformer flux (Volt-second) differences between the
even and odd half-cycles in the FB topology and it is applied only to the odd half-cycle.
As shown in
, the duty cycle components are multiplied by ramp_max to convert from duty cycle to
pulse width, ramp_pw. The pulse width is then converted to target t1 and t2 values, t1_val and t2_val, based on
the modulation type as show in
Table 42
t1 and t2 computation by edge modulation type
Modulation type
t1_val
t2_val
Dual edge (DE)
(ramp_max - ramp_pw) / 2
(ra ramp_pw) / 2
Leading edge (LE)
ramp_max - ramp_pw
ramp_max
Trailing edge (TE)
0
ramp_pw
The target t1 and t2 values are then compared against the ramp waveform to create the t1_crossing and
t2_crossing signals used by the pulse generators to define the PWM edges, as described in
Duty-cycle lock mode is intended for use in FB topologies where it is important to maintain the flux balance
between the two half-cycles. In this mode, the odd half-cycle PW is sampled and held on the even half-cycle t2
crossing detection. In the case of TE modulation t1 = 0 and this leads to equal odd and even cycle PWs based on
the contributions from the compensator (PID) and current balance. The duty-cycle lock mode is enabled by
setting the register
rampX_dutyc_lock
to 1.
It should be noted that the flux balance adjustment still contributes to the odd cycle PW even when duty-cycle
lock is enabled. This means that the PWs will not be identical if compensation is required to correct some
external deviation (e.g., differences in driver PW propagation).
pid_duty
S
ibal_duty_adj
+
+
0
1
ramp_force_duty
ramp_force_duty_en
X
ramp_max
pw_even
S
X
ramp_max
flux_duty_adj
pw_odd
0
1
0
1
ramp_pw
ramp_dutyc_lock
even_cycle
ramp_half_mode
pulse
width
to
t1,t2
ramp_m_flavor
t1_val
t2_val
ramp
cross
detect
t1_crossing
t2_crossing
Ramp
ramp
even_cycle
Hold
ramp_force_t1, ramp_force_t1_en
ramp_force_t2, ramp_force_t2_en
