Infineon XDPP1100, Technical Reference Manual

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User Manual 112 of 562 V 1.0
2021-08-25
XDPP1100 technical reference manual
Digital power controller
Compensator
The compensation filter output, duty_cycle, is clamped to a fixed 16-bit width. In the case of VMC it refers a
value between 0.0 and 1.0. The PCMC behavior and the corresponding compensator output value is discussed
in
section 6.3 .
6.1.5 Output override – forced duty cycle
The PID output of the compensation filter can be overridden. The user can force the duty-cycle value by
selecting:
•
Register pid_force_duty_en
•
Then setting a value in register pid_force_duty
This functionality is illustrated in the post-filter block diagram in Figure 50 .
Because this override is applied at the PID output, downstream adjustments to the duty cycle are still applied.
These adjustments include:
•
Current balance in an interleaved (multiphase) design
•
Flux balance in a FB design
However, if the downstream adjustments are required to be overridden, a separate pair of override registers is
provided:
•
ramp0_force_duty
•
ramp1_force_duty
These functions are discussed in more detail in section 7.3.4 .
6.1.6 Coefficient scaling
The PID coefficients are scaled with V
RECT
in order to maintain constant loop gain despite the input voltage
variations. The user can define a reference V
RECT
voltage through register pid_vrect_ref , at which the gain scale
is 1.0. This coefficient scale factor is defined as given in Equation (6.26).
𝐶𝑜𝑒𝑓𝑓𝑖𝑐𝑖𝑒𝑛𝑡 𝑠𝑐𝑎𝑙𝑒 𝑓𝑎𝑐𝑡𝑜𝑟 =
𝑉
𝑅𝐸𝐶𝑇
𝑝𝑖𝑑_𝑣𝑟𝑒𝑐𝑡_𝑟𝑒𝑓
(6.26)
The register
pid_vrect_ref value should be set to the expected nominal V
RECT
voltage prior to the PID coefficient
optimization.
An example for selecting a proper
pid_vrect_ref value is given below for a FB topology with nominal input
voltage of 48 V and transformer turns ratio of 3. The nominal rectified voltage is computed in Equation (6.27)
and the resulting value should be set via register
pid_vrect_ref .
𝑉
𝑅𝐸𝐶𝑇−𝑛𝑜𝑚
=
𝑉
𝐼𝑁−𝑛𝑜𝑚
𝑁
𝑡𝑢𝑟𝑛𝑠
=
48 𝑉
3
= 16 𝑉
(6.27)
Subsequently, the optimized PID coefficients can be observed from registers:
•
pid_kp_eff , for K
P
•
pid_ki_eff , for K
I
•
pid_kd_eff , for K
D
6.1.7 Freeze, reset accumulator
Undesired integrator “windup” could occur in the following operating condit ions:
•
Burst mode (BM) operation, when PID is not controlling the output duty cycle.