User Manual 558 of 562 V 1.0
2021-08-25
XDPP1100 technical reference manual
Digital power controller
Central processing unit subsystem
15.14.1
Serial wire debugger interface
SWD interface has two signals:
•
SWCLK
–
input serial clock
•
SWDIO
–
bidirectional serial data
The serial clock line is generally driven by the external host. Clock speed is fixed for all the transactions of a
debug session and depends on target-specific implementation (it can normally be configured from 1 MHz to 20
MHz).
XDPP1100 can achieve up to 20 MHz clock speed for SWCLK, but because SWCLK is asynchronous with respect
to any internal device clock and proper synchronizations are in place in the Cortex® DAP, it is important that a
minimum division ratio of 4 is maintained between the internal core clock and the debugger clock itself. That
means that 20 MHz can be achieved when the core clock is at its nominal 100 MHz frequency, but it should be
reduced if the core clock is running at a lower speed.
The serial data line has to be driven both by the debugger and XDPP1100 (bidirectional communication
protocol), to avoid contention. The SWD protocol defines slots for data transmitting/receiving and turnaround
periods.
The host driving the line low, when the clock is applied, is interpreted by the target as
“
idle cycle
”
.
On the XDPP1100, due to IO limitations, SWD pins are shared with other functionalities (as alternate functions),
and because debug is not an application function, they are by default not available at power-up during a
functional boot.
The relevant pins for the SWD interface are described in
Table 119
Debugger interface pin mapping
Pin name
XDPP1100-Q040
Pin number
XDPP1100-Q024
Pin number
Debug
function
Description
XADDR1
7
5
TEST_GATE
To detect and enter debug mode
SYNC
38
22
SWCLK
Serial clock
PWRGD
40
24
SWDIO
Serial bidirectional data
The XADDR1
’s
primary role, in functional mode, is to measure an external resistor to select the configuration
address for the I
2
C/PMBus interface.
But XADDR1, if kept at 3.3 V during power-up, enables the debugger interface to be available on SYNC and
PWRGD IOs (configuring the multiplexer that selects SWCLK on SYNC and SWDIO on PWRGD).
The XADDR1 is latched to 250 µs after power-on-reset, so in order to have a stable value during the latching
phase, it has to be kept at 3.3 V before the power-up of the XDPP1100 3.3 V supply.
After the latching phase, the value is maintained until a chip power-down or a chip reset occurs, so XADDR1 can
be reprogrammed by FW for other functionalities.
The circuit to implement this feature is shown in
