User Manual
155 of 562
V 1.0
2021-08-25
XDPP1100 technical reference manual
Digital power controller
Digital pulse width modulator
Peripheral Field name
Access Address
Bits
Description
(or 0.25 * T
switch
and 0.75 * T
switch
for
bridge topologies) and both are
modulated. Odd and even cycle
designations are for use with bridge
topologies to distinguish between
half-cycles.
0: t1
1: t2
2: t1 even cycle
3: t2 even cycle
4: t1 odd cycle
5: t2 odd cycle
6: t1 delay
7: t2 delay
pwm
pwm5_rise_sel
RW
7000_2C08h [6:3]
Topology-driven PWM5 rising edge
select. t1 and t2 refer to the
modulated edges created by the
ramp. When using TE modulation,
t1 is fixed at time 0 and t2 is
modulated. When using LE
modulation, t2 is fixed at T
switch
(or
0.5 * T
switch
and T
switch
for bridge
topologies) and t1 is modulated.
When using DE modulation, t1 and
t2 are centered around 0.5 * T
switch
(or 0.25 * T
switch
and 0.75 * T
switch
for
bridge topologies) and both are
modulated. Odd and even cycle
designations are for use with bridge
topologies to distinguish between
half-cycles.
The VRSEN and BVRSEN options
allow a PWM output to be set high
after detection of the falling
transition of the rectification
voltage.
0: t1
1: t2
2: t1 even cycle
3: t2 even cycle
4: t1 odd cycle
5: t2 odd cycle
6: t1 delay
7: t2 delay
8: VRSEN neg. edge
9 to 15: BVRSEN neg. edge
pwm
pwm6_fall_sel
RW
7000_2C08h [9:7]
Topology-driven PWM6 falling edge
select. t1 and t2 refer to the
modulated edges created by the
ramp. When using TE modulation,
