User Manual 479 of 562 V 1.0
2021-08-25
XDPP1100 technical reference manual
Digital power controller
Central processing unit subsystem
15.6.4
DMA registers
The relevant DMA-related registers and their descriptions are provided in
Table 105
DMA-related register description
Register name Field name
Access Address
Bits
Description
DMA_STATUS
MASTER_ENABLE
R
5000_0000h [0]
Enable status of the controller.
0: Controller is disabled
1: Controller is enabled
DMA_STATUS
RES0
R
5000_0000h [3:1]
Reserved
DMA_STATUS
STATE
R
5000_0000h [7:4]
Current state of the control state
machine. State can be one of the
following bit combinations (values
not listed are undefined):
0: Idle
1: Reading channel controller date
2: Reading source data end pointer
3: Reading destination data end
pointer
4: Reading source data
5: Writing destination data
6: Waiting for DMA request to clear
7: Writing channel controller data
8: Stalled
9: Done
10: Peripheral scatter-gather
transition
DMA_STATUS
RES1
R
5000_0000h [15:8]
Reserved
DMA_STATUS
CHNLS_MINUS1
R
5000_0000h [20:15] Returns the number of available
channels minus 1. For example:
0: 1 available channel
15: 16 available channels
DMA_STATUS
RES2
R
5000_0000h [31:21] Reserved
DMA_CFG
MASTER_ENABLE
W
5000_0004h [0]
Enable for the controller.
0: Disable controller
1: Enable controller
DMA_CFG
RES0
W
5000_0004h [4:1]
Reserved, write as 0.
DMA_CFG
CHN1_PROT_CTRL W
5000_0004h [7:5]
Sets the AHB-Lite protection by
controlling the HPROT[3:1] signal
levels as follows:
[2] Controls HPROT[3] to indicate if
a cacheable access is occurring
[1] Controls HPROT[2] to indicate if
a bufferable access is occurring
