User Manual
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V 1.0
2021-08-25
XDPP1100 technical reference manual
Digital power controller
Compensator
•
pid_kp_index_1ph
for K
P
•
pid_ki_index_1ph
for K
I
•
pid_kd_index_1ph
for K
D
The PID provides a pole in the origin and two mid-band zeros while the LPFs present two high-frequency poles.
This corresponds to the Type III compensation response which can provide up to 180 degrees of phase boost. A
typical Type III compensator gain is illustrated in
, where f
z1
, f
z2
, f
p1
and f
p2
represent the pole and zero
frequencies.
Figure 46
Typical Type III compensator gain
6.1.1
Pre-filter
The pre-filter is a single-pole LPF, implemented as shown in
, and it consists of:
•
One input, the error voltage V
errn
•
Two outputs, verrn_filt and verrn_slope
The verrn_filt is the low-pass filtered version of the computed error, V
errn
, and it is used by the proportional and
integral terms of the PID. The second output, verrn_slope, is the derivative of the filtered error and it is used by
the derivative term of the PID.
Figure 47
Pre-filter block diagram
The pre-filter creates the first high-frequency pole, f
p1
, in the compensator transfer function. The pole location
(i.e., LPF BW) is defined by the filter coefficient K
FP1
, which is programmed via register
pid_kfp1_index_1ph
.
fz1
fz2
fp2
fp1
M
ag
ni
tu
de
(dB
)
Frequency (Hz)
Verrn
Clamp
D
Q
Clamp
D
Q
Clamp
D
Q
Verrn_filt
Verrn_slope
S9.10
S10.10
Kfp1
U-3.13
S1.23
S10.23
S5.10
S9.10
S9.6
S10.6
S9.6
S8.6
S8.6
S9.3
S9.3
+
-
+
+
+
-
S9.3
