Infineon XDPP1100, Technical Reference Manual

Page: 360 / 562

User Manual 360 of 562 V 1.0
2021-08-25
XDPP1100 technical reference manual
Digital power controller
Central processing unit subsystem
Register name Field name Access Address Bits Description
Note: The primary clock gating is
performed if this bit is set.
KILL_ME_SOFTLY bit of the
HOSC_SW_CLK_GATING_CTRL
register is also set. Be sure to
enable an external wakeup source
before executing the primary clock
gating procedure (i.e., entering the
hibernate state) in order to avoid
permanent loss of the CPUS clock.
0: Status of
“ hosc_clk ” clock is not
affected
1: Enable
“ hosc_clk ” clock
CLK_EN_CTRL
_SET rom_clk_g W 4000_2030h [1] Enable the rom_clk clock.
0: Status of
“ rom_clk ” clock is not
affected
1: Enable
“ rom_clk ” clock
CLK_EN_CTRL
_SET ram1_clk_g W 4000_2030h [2] Enable the ram1_clk clock.
0: Status of
“ ram1_clk ” clock is not
affected
1: Enable
“ ram1_clk ” clock
CLK_EN_CTRL
_SET ram2_clk_g W 4000_2030h [3] Enable the ram2_clk clock.
0: Status of ‘ram2_clk’ clock is not
affected
1: Enable ‘ram2_clk’ clock
CLK_EN_CTRL
_SET amba_clk_g W 4000_2030h [4] Enable the amba_clk clock.
0: Status of
“ amba_clk ” clock is not
affected
1: Enable
“ amba_clk ” clock
CLK_EN_CTRL
_SET dma_clk_g W 4000_2030h [5] Enable the dma_clk clock.
0: Status of
“ dma_clk ” clock is not
affected
1: Enable
“ dma_clk ” clock
CLK_EN_CTRL
_SET cnfg_otp1_w_clk_g W 4000_2030h [6] Enable the cnfg_otp1_w_clk clock.
0: Status of
“ cnfg_otp1_w_clk ”
clock is not affected
1: Enable
“ cnfg_otp1_w_clk ” clock
CLK_EN_CTRL
_SET cnfg_dma_clk_g W 4000_2030h [10] Enable the cnfg_dma_clk clock.
0: Status of
“ cnfg_dma_clk ” clock is
not affected
1: Enable
“ cnfg_dma_clk ” clock
CLK_EN_CTRL
_SET bif_reg_clk_g W 4000_2030h [11] Enable the bif_reg_clk clock.
0: Status of
“ bif_reg_clk ” clock is
not affected