Infineon XDPP1100, Technical Reference Manual

Page: 363 / 562

User Manual 363 of 562 V 1.0
2021-08-25
XDPP1100 technical reference manual
Digital power controller
Central processing unit subsystem
Register name Field name Access Address Bits Description
0: Status of “ hosc_clk ” clock is not
affected
1: Disable
“ hosc_clk ” clock
CLK_EN_CTRL
_CLR rom_clk_g W 4000_2034h [1] Disable the rom_clk clock.
0: Status of
“ rom_clk ” clock is not
affected
1: Disable
“ rom_clk ” clock
CLK_EN_CTRL
_CLR ram1_clk_g W 4000_2034h [2] Disable the ram1_clk clock.
0: Status of ‘ram1_clk’ clock is not
affected
1: Disable ‘ram1_clk’ clock
CLK_EN_CTRL
_CLR ram2_clk_g W 4000_2034h [3] Disable the ram2_clk clock.
0: Status of
“ ram2_clk ” clock is not
affected
1: Disable
“ ram2_clk ” clock
CLK_EN_CTRL
_CLR amba_clk_g W 4000_2034h [4] Disable the amba_clk clock.
0: Status of
“ amba_clk ” clock is not
affected
1: Disable
“ amba_clk ” clock
CLK_EN_CTRL
_CLR dma_clk_g W 4000_2034h [5] Disable the dma_clk clock.
0: Status of
“ dma_clk ” clock is not
affected
1: Disable
“ dma_clk ” clock
CLK_EN_CTRL
_CLR cnfg_otp1_w_clk_g W 4000_2034h [6] Disable the cnfg_otp1_w_clk clock.
0: Status of
“ cnfg_otp1_w_clk ”
clock is not affected
1: Disable
“ cnfg_otp1_w_clk ” clock
CLK_EN_CTRL
_CLR cnfg_dma_clk_g W 4000_2034h [10] Disable the cnfg_dma_clk clock.
0: Status of
“ cnfg_dma_clk ” clock is
not affected
1: Disable
“ cnfg_dma_clk ” clock
CLK_EN_CTRL
_CLR bif_reg_clk_g W 4000_2034h [11] Disable the bif_reg_clk clock.
0: Status of
“ bif_reg_clk ” clock is
not affected
1: Disable
“ bif_reg_clk ” clock
CLK_EN_CTRL
_CLR bif_per_svid_clk_g W 4000_2034h [12] Disable the bif_per_svid_clk clock.
Note: The CRC32 peripheral is using
the SVID slot so this actually
controls the CRC32 clock.
0: Status of
“ bif_per_svid_clk ”
clock is not affected
1: Disable
“ bif_per_svid_clk ” clock
CLK_EN_CTRL
_CLR bif_per_pmbus_clk
_g W 4000_2034h [13] Disable the bif_per_pmbus_clk
clock.