User Manual 495 of 562 V 1.0
2021-08-25
XDPP1100 technical reference manual
Digital power controller
Central processing unit subsystem
15.9.1
Dual-timer block diagram
The dual-timer block diagram is shown in
Figure 114
Dual-timer block diagram
15.9.2
Dual-timer registers
The relevant D
TIMER
-related registers and their descriptions are provided in
Table 108
D
TIMER
-related register descriptions.
Register name Field name
Access Address
Bits
Description
TIM_SEQ0_TIM
ERLOAD
LOAD
RW
6001_0000h
6002_0000h
6003_0000h
[31:0]
TIM_SEQ0_TIMERLOAD contains
the value from which the counter is
to decrement. This is the value
used to reload the counter when
periodic mode is enabled and the
current count reaches zero.
When this register is written to
directly, the current count is
immediately reset to the new value
at the rising edge of the enabled
clock.
The value in this register is also
overwritten if the
TIM_SEQ0_TIMERBGLOAD register
is written to, but the current count
is not immediately affected.
If values are written to both the
TIM_SEQ0_TIMERLOAD and
TIM_SEQ0_TIMERBGLOAD registers
before an enabled rising edge on
TIMCLK, the following occurs:
On the next enabled clock edge, the
value written to the
Dual Input Timer
Identitification
registers
Test
integration
registers
Read data
generation
Free running
counter 1
Address
decoder
TIMINTC
generation
Free running
counter 2
