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User Manual 429 of 562 V 1.0
2021-08-25
XDPP1100 technical reference manual
Digital power controller
Central processing unit subsystem
Register name Field name
Access Address
Bits
Description
1: OTP
2: RAM1
3: RAM2
MMU_LUT_RO
M61_DATA
PROT
RW
4000_40F4h [0]
Defines the write protection of the
target address block in the target
memory space. Any write attempt
to a protected block will result in an
illegal access fault.
0: Disable write protection
1: Enable write protection
MMU_LUT_RO
M61_DATA
BLK_ADR
RW
4000_40F4h [7:1]
Defines the target address block
into which the ROM section is
remapped.
MMU_LUT_RO
M61_DATA
BASE_ADR
RW
4000_40F4h [9:8]
Defines the target memory space
into which the ROM section is
remapped.
0: ROM
1: OTP
2: RAM1
3: RAM2
MMU_LUT_RO
M62_DATA
PROT
RW
4000_40F8h [0]
Defines the write protection of the
target address block in the target
memory space. Any write attempt
to a protected block will result in an
illegal access fault.
0: Disable write protection
1: Enable write protection
MMU_LUT_RO
M62_DATA
BLK_ADR
RW
4000_40F8h [7:1]
Defines the target address block
into which the ROM section is
remapped.
MMU_LUT_RO
M62_DATA
BASE_ADR
RW
4000_40F8h [9:8]
Defines the target memory space
into which the ROM section is
remapped.
0: ROM
1: OTP
2: RAM1
3: RAM2
MMU_LUT_RO
M63_DATA
PROT
RW
4000_40FCh [0]
Defines the write protection of the
target address block in the target
memory space. Any write attempt
to a protected block will result in an
illegal access fault.
0: Disable write protection
1: Enable write protection