User Manual
22 of 562
V 1.0
2021-08-25
XDPP1100 technical reference manual
Digital power controller
Voltage sense
•
V
RECT
Therefore, while operating in V
RECT
mode, the tracking ADC only tracks the input when the input voltage is
reflected to the secondary-side V
RECT
. This occurs when the primary-side PWM signal
is high or “
on
”
. Note that
the identification of the PWM and SR FET PWM outputs is through registers:
•
ce_on_mask0
•
ce_on_mask1
•
ce_off_mask0
•
ce_off_mask1
These settings are discussed in
2.3.2.1
V
RECT
timing for single PWM signal
The rectified voltage is pulsating, and therefore its measurement is not as straightforward as in the case of V
OUT
.
The measurement cycle timing is initiated when the primary-side PWM signal goes high. At this point, a timer is
started and the XDPP1100 waits for a high transition on the VRSEN or BVSEN_BVRSEN input pin. The rising edge
of the rectified voltage is detected via a comparator, vrs_comp. It is clocked at 200 MHz and has a
programmable threshold via register
vrs_cmp_ref_sel
. When V
RECT
exceeds this threshold, the comparator
enters its hold phase of operation.
Once the transition is detected,
the tracking ADC’s DAC is
preloaded to its value during the previous cycle
before the PWM signal transitioned low. The tracking ADC then waits for a user-programmable time (register
vrs_track_start_thr
) measured from the PWM rising edge. Subsequent to the timer completion, the tracking
ADC begins tracking the input voltage and the tracking continues until falling-edge PWM is detected. The
current-tracking DAC code is then saved for the next cycle. The complete V
RECT
measurement cycle timing is
shown in
Figure 11
Timing of the V
RECT
measurement cycle
PWM
VRSEN
vrs_comp_ref
vrs_comp
Hold Time
Tracking
Window
Watchdog
Timeout
vrs_cmp_wdt_thr
Tracking ADC active
vrs_track_start_thr
Tracking ADC DAC held at code 0
Tracking ADC DAC held at last sample
taken at PWM falling edge
