Infineon XDPP1100, Technical Reference Manual

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User Manual 359 of 562 V 1.0
2021-08-25
XDPP1100 technical reference manual
Digital power controller
Central processing unit subsystem
Register name Field name Access Address Bits Description
1: Clock “ dtimer3_clk ” is gated
when CM0 is in deep sleep state
CLK_DEEP_SL
EEP_MSK_CNF
G
dse_wdt_clk_g RW 4000_2018h [20]
Enable wdt_clk clock gating when
Cortex®-M0 enters deep sleep state.
0: Clock
“ wdt_clk ” is not gated by
CM0 power state status
1: Clock
“ wdt_clk ” is gated when
CM0 is in deep sleep
CLK_DEEP_SL
EEP_MSK_CNF
G dse_gpio0_clk_g RW 4000_2018h [21] Enable gpio0_clk clock gating when
Cortex®-M0 enters deep sleep state.
0: Clock
“ gpio0_clk ” is not gated by
CM0 power state status
1: Clock
“ gpio0_clk ” is gated when
CM0 is in deep sleep state
CLK_DEEP_SL
EEP_MSK_CNF
G dse_gpio1_clk_g RW 4000_2018h [22] Enable gpio1_clk clock gating when
Cortex®-M0 enters deep sleep state.
0: Clock
“ gpio1_clk ” is not gated by
CM0 power state status
1: Clock
“ gpio1_clk ” is gated when
CM0 is in deep sleep state
HOSC_SW_CL
K_GATING_CT
RL kill_me_softly RW 4000_201Ch [0] Enable hosc_clk SW clock gating.
Note: The primary clock gating is
performed if this bit is set and the
hosc_clk_g bit of the CLK_EN_CTRL
register is also set or if this bit is set
and one of the sleep mask bit-0s
are set when executing the
WFI/WFE instruction. Be sure to
enable an external wakeup source
before executing the primary clock
gating procedure (i.e., entering the
hibernate state) in order to avoid
permanent loss of the CPUS clock.
0: Clock
“ hosc_clk ” cannot be
gated
1: Clock
“ hosc_clk ” can be gated
HOSC_HW_CL
K_GATING_CT
RL kill_me_hardly RW 4000_2020h [0] Enable hosc_clk HW clock gating by
CPUS_EN signal.
0: Clock
“ hosc_clk ” cannot be
gated
1: Clock
“ hosc_clk ” can be gated
SPARE_FF SPARE_FF RW 4000_2024h [31:0] Spare register
CLK_EN_CTRL
_SET hosc_clk_g W 4000_2030h [0] Enable bit for the clock hosc_clk if
the hosc_clk primary clock gating
control has been enabled.