User Manual
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V 1.0
2021-08-25
XDPP1100 technical reference manual
Digital power controller
Voltage sense
Figure 17
Dead time counters
If the counter detects the incoming waveform edges in the incorrect order, it will indicate this through the
following status registers:
•
For VS module 1:
vsp1_vrsr_b4_srf
indicates VRSEN detected VRS comp rising edge before SR FET falling
edge, and
vsp1_srr_b4_vrsf
indicates VRSEN detected SR FET rising edge before VRS comp falling edge.
•
For VS module 2:
vsp2_vrsr_b4_srf
indicates BVRSEN detected VRS comp rising edge before SR FET falling
edge, and
vsp2_srr_b4_vrsf
indicates BVRSEN detected SR FET rising edge before VRS comp falling edge.
2.3.3
V
IN
processing
The VS modules VS1 and VS2 with sense pins VRSEN and BVRSEN, respectively, can be configured to measure
the primary-side input voltage, V
IN
, directly. This is obtained by:
•
Selecting the input voltage source (VRSEN) or (BVRSEN) with register
tlm_vin_src_sel
•
Selecting general-purpose ADC mode (0) via register
vsp1_vrs_sel
for VRSEN, or V
OUT
sense mode (0) via
vsp2_vrs_sel
for BVRSEN
When the VS module is configured to sense the input voltage from the primary side, the vsp_vrect output is
continuous, not pulsating as in the case of sensing V
RECT
.
2.4
VS registers
All VS-related registers and their descriptions are provided in
Table 2
VS-related register descriptions
Peripheral Field name
Access Address
Bits
Description
analog
vs0_step
RW
7000_0400h [2:0]
VS0 (VSEN) ADC tracking loop
integrator step size when
automatic step size disabled.
Recommended setting is 1 for
highest resolution.
analog
vs0_step_en
RW
7000_0400h [3]
VS0 (VSEN) tracking loop step size
control.
0: Automatic step size
PWM
SR
VRSEN
vrs_comp_ref
vrs_comp
vspX_cnt_srf2vrsr
vspX_cnt_srf_avg
vspX_cnt_vrsf2srr
vspX_cnt_srr_avg
vspX_cnt_vrscomp_e
vspX_cnt_vrscomp_o
