User Manual 509 of 562 V 1.0
2021-08-25
XDPP1100 technical reference manual
Digital power controller
Central processing unit subsystem
15.10.4
PMBus registers
The relevant PMBus-related registers and their descriptions are provided in
Table 109
PMBus-related register descriptions
Register name Field name
Access Address
Bits
Description
STATUS
BUSY
R
7008_0000h [0]
Reflects the status of the finite state
machine (FSM).
0: FSM is in idle state
1: FSM is not in idle state
STATUS
DIRECTION
R
7008_0000h [1]
Reflects the status of the
transaction direction (this is
correlated to the slave address if
bit_cnt == 7).
0: Operation bit is set to write
1: Operation bit is set to read
STATUS
ACK_STATUS
R
7008_0000h [2]
Reflects the status of ACK_NACK at
the interrupt generation.
0: NACK
1: ACK
STATUS
TOO_FEW_BITS
R
7008_0000h [3]
Reflects the flag status indicating a
transaction termination not aligned
to the byte.
0: All transactions have been
aligned to bytes
1: Transaction not aligned to bytes
STATUS
BIT_CNT
R
7008_0000h [7:4]
Current number of received or
transmitted bits since last
interrupt.
STATUS
BYTE_CNT_RX
R
7008_0000h [15:8]
Current numbers of received bytes
since start event.
STATUS
BYTE_CNT_TX
R
7008_0000h [23:16] Current numbers of transmitted
bytes since start event.
STATUS
BUS_CONTENTION R
7008_0000h [24]
Reflects the bus contention status
of the last TX transaction
performed.
0: Bus contention did not occur
1: Bus contention occurred
STATUS
TOO_LONG_SCL_S
TRETCH
R
7008_0000h [25]
SCL clock stretching timeout.
0: No timeout occurred
1: The SCL clock has been internally
stretched more than the
programmed timeout
STATUS
SCL_IN
R
7008_0000h [26]
Status of the debounced SCL input
signal.
0: SCL_IN is at low level
