Infineon XDPP1100, Technical Reference Manual

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User Manual 135 of 562 V 1.0
2021-08-25
XDPP1100 technical reference manual
Digital power controller
Digital pulse width modulator
Figure 58 Typical pwmX_loop_map, pwmX_rise_sel and pwmX_fall_sel settings for various topologies
7.2.4 Dead time programming
The XDPP1100 is capable of applying independent dead time (delay) to both the rising and the falling edges of
each PWM output. The dead time programming for the edges is the following:
•
Rising edge dead time, via register pwmY_dr (Y = 1 to 12)
•
Falling edge dead time, via pwmY_df
Figure 59 illustrates the dead time programming, where both parameters have a range of 0.0 to 318.75 ns with
the resolution of 1.25 ns. The settings for all pwmY_dr and pwmY_df are automatically computed based on the
programming of PMBus command PWM_DEADTIME. The mapping from PWM_DEADTIME to each pwmY_dr and
pwmY_df is shown in Table 40 .
Ramp 0
Ramp 1
programmed with 180
degree shift
ramp0_t1
ramp0_t2
ramp1_t1
ramp1_t2
t1 even
t2 even
t1 odd
t2 odd
t1 even
t2 even
t1 even
t2 even
t1 odd
t2 odd
t1 even
t2 odd
pwmY_loop_map[1:0] = 1 (ramp 0)
pwmY_rise_sel[2:0] = 0 (t1)
pwmY_fall_sel[2:0] = 1 (t2)
pwmY_loop_map[1:0] = 1 (ramp 0)
pwmY_rise_sel[2:0] = 1 (t2)
pwmY_fall_sel[2:0] = 0 (t1)
pwmY_loop_map[1:0] = 1 (ramp 0)
pwmY_rise_sel[2:0] = 2 (t1 even)
pwmY_fall_sel[2:0] = 3 (t2 even)
pwmY_loop_map[1:0] = 1 (ramp 0)
pwmY_rise_sel[2:0] = 4 (t1 odd)
pwmY_fall_sel[2:0] = 5 (t2 odd)
pwmY_loop_map[1:0] = 1 (ramp 0)
pwmY_rise_sel[2:0] = 3 (t2 even)
pwmY_fall_sel[2:0] = 2 (t1 even)
pwmY_loop_map[1:0] = 1 (ramp 0)
pwmY_rise_sel[2:0] = 5 (t2 odd)
pwmY_fall_sel[2:0] = 4 (t1 odd)
pwmY_loop_map[1:0] = 1 (ramp 0)
pwmY_rise_sel[2:0] = 2 (t1 even)
pwmY_fall_sel[2:0] = 4 (t1 odd)
pwmY_loop_map[1:0] = 1 (ramp 0)
pwmY_rise_sel[2:0] = 3 (t2 even)
pwmY_fall_sel[2:0] = 5 (t2 odd)
pwmY_loop_map[1:0] = 1 (ramp 0)
pwmY_rise_sel[2:0] = 5 (t2 odd)
pwmY_fall_sel[2:0] = 3 (t2 even)
pwmY_loop_map[1:0] = 1 (ramp 0)
pwmY_rise_sel[2:0] = 4 (t1 odd)
pwmY_fall_sel[2:0] = 2 (t1 even)
typical buck,
forward, ACF
settings
typical HB, FB
primary
settings
typical HB,
FB, PSFB
secondary
settings
typical
PSFB
primary
settings
pwmY_loop_map[1:0] = 2,3 (ramp 1)
pwmY_rise_sel[2:0] = 0 (t1)
pwmY_fall_sel[2:0] = 1 (t2)
pwmY_loop_map[1:0] = 2,3 (ramp 1)
pwmY_rise_sel[2:0] = 1 (t2)
pwmY_fall_sel[2:0] = 0 (t1)
typical Loop 1
or interleave
phase buck,
forward, ACF
settings