User Manual 548 of 562 V 1.0
2021-08-25
XDPP1100 technical reference manual
Digital power controller
Central processing unit subsystem
Register name Field name
Access Address
Bits
Description
1: Even parity. The UART generates
or checks for an even number of 1s
in the data and parity bits.
UARTLCR_H
STP2
RW
700C_002Ch [3]
Two stop bits select. If this bit is set
to 1, two stop bits are transmitted
at the end of the frame. The receive
logic does not check for two stop
bits being received.
UARTLCR_H
FEN
RW
700C_002Ch [4]
Enable FIFOs.
0: FIFOs are disabled (character
mode); that is, the FIFOs become 1-
byte-deep holding registers
1: Transmit and receive FIFO
buffers are enabled (FIFO mode)
UARTLCR_H
WLEN
RW
700C_002Ch [5]
Word length. These bits indicate
the number of data bits transmitted
or received in a frame as follows:
0: 5 bits
1: 6 bits
2: 7 bits
3: 8 bits
UARTLCR_H
SPS
RW
700C_002Ch [7]
Stick parity select. This bit has no
effect when the PEN bit disables
parity checking and generation.
0: Low stick parity is disabled
1: High either:
If the EPS bit is 0 then the parity bit
is transmitted and checked as a 1
Or if the EPS bit is 1 then the parity
bit is transmitted and checked as a
0
UARTCR
UARTEN
RW
700C_0030h [0]
UART enable.
0: UART is disabled. If the UART is
disabled in the middle of
transmission or reception, it
completes the current character
before stopping.
1: UART is enabled. Data
transmission and reception occurs
for either UART signals or SIR
signals depending on the setting of
the SIREN bit.
UARTCR
SIREN
RW
700C_0030h [1]
SIR enable. This bit has no effect if
the UARTEN bit disables the UART.
